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引用次数: 3
摘要
本文提出了一种采用多米诺比较器结构的6位1.6 gs /s SAR ADC。所提出的多米诺骨牌sar结构有效地提高了ADC的运算速度。为了进一步加快操作速度，采用乒乓操作，达到1.6-GS/s。针对PVT的变化，提出了一种自适应采样器来自动调整分配的转换时间。该ADC采用55nm LP CMOS实现。它从1.2 v电源消耗5兆瓦。在Nyquist-rate下，模拟SNDR和SFDR分别为35.4和52 dB。它的ENOB是5.6位，相当于64 fJ/转换步长的FOM。
This paper presents a 6-bit 1.6-GS/s SAR ADC incorporating a domino-comparator architecture. The proposed domino-SAR architecture effectively speed up ADC operation. To further fasten the operating speed, a ping-pong operation is applied to achieve 1.6-GS/s. To against PVT variations, an adaptive sampler is proposed to adjust the allocated conversion time automatically. The ADC was implemented in 55nm LP CMOS. It consumes 5 mW from a 1.2-V supply. At Nyquist-rate, the simulated SNDR and SFDR are 35.4 and 52 dB respectively. Its ENOB is 5.6 bits, equivalent to a FOM of 64 fJ/conv.-step.
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