采用降噪网络技术的超低噪声LDO设计

2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI:10.1109/ISOCC.2017.8368850

Hamed Abbasizadeh, B. S. Rikan, Thi Kim Nga Truong, Kwan-Tae Kim, Sungjin Kim, Dongsoo Lee, Kangyoon Lee

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引用次数: 5

摘要

本文提出了一种用于射频应用供电的超低噪声低差(LDO)稳压器。本文提出的LDO在带隙基准(BGR)的输出和LDO的输出与反馈电阻节点(图1中的VFB)之间采用了两个内部降噪网络，以实现兴趣频率下的超低噪声。采用5位控制电阻阶梯来补偿过程、电压和温度(PVT)的变化。LDO的输出电压等级可从1.05 V到2.6 V，微调步进为50 mV。在10khz时，LDO的最高输出噪声为64.52 nV/VHz。该LDO采用CMOS 55nm工艺实现，芯片尺寸为480 μm × 330 μm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A design of ultra-low noise LDO using noise reduction network techniques

This paper presents an ultra-low noise low-dropout (LDO) regulators for powering RF applications. The proposed LDO employs two internal noise reduction network at the output of the bandgap reference (BGR), and between output and feedback resistors node (VFB in Fig. 1) of LDO to achieve ultra-low noise at interest frequencies. The 5-bits controlled resistor ladder is adopted to compensate the process, voltage, and temperature (PVT) variations. The output voltage level of LDO can be from 1.05 V to 2.6 V with trimming step of 50 mV. The highest output noise of the LDO is 64.52 nV/VHz at 10 KHz. The proposed LDO is implemented in CMOS 55 nm technology with the die size of 480 μm × 330 μm.

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2017 International SoC Design Conference (ISOCC)

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