多通道多千兆PRBS发生器，内置时钟，采用0.18 μm CMOS技术

2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI:10.1109/ISOCC.2017.8368893

Chi-Hsien Wu, Jau‐Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu

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引用次数: 3

摘要

本文采用0.18μm CMOS工艺设计了一种内置时钟的并行伪随机比特序列(PRBS)产生电路。为了实现高速运行，电路中采用了电流模式逻辑(CML)。在PRBS发生器中，可以产生4路2gb /s和2路4gb /s的PRBS信号。该芯片在1.8 v电源下的功耗为554.3 mw，芯片面积为1.196×1.01-mm2。PRBS发生器适用于多级调制和多通道传输测试。

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Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology

In this paper, a parallel pseudo-random bit sequence (PRBS) generator circuit with a built-in clock was designed in 0.18μm CMOS Technology. For high-speed operation, the current-mode logic (CML) was used in the circuit. In the PRBS generator, four-channel 2-Gb/s and two-channel 4-Gb/s PRBS signals can be generated. The power consumption of the chip is 554.3-mW at 1.8-V of power supply, and the chip area is 1.196×1.01-mm2. The PRBS generator can be suitable in multi-level modulation and multi-channel transmission tests.

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2017 International SoC Design Conference (ISOCC)

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