Low-area implementations of concurrent error detection logarithmic processors

Abstract

In this paper, low-area implementations of concurrent error detection (CED) logarithmic processors are proposed. By adopting our logarithmic/anti-logarithmic converters with same functions having different architectures, the proposed schemes can perform logarithm-based multiplications/divisions with CED ability. Simulation results show that our proposed CED logarithmic processors can outperform conventional multipliers/dividers in terms of delay and area, which are more suitable for real-time computations with CED ability.