A design of ultra low power I2C synchronous slave controller with interface voltage level independency in 180 nm CMOS technology

In this paper, an ultra low power I2C synchronous slave controller (I2CSSC) is presented for low data rate communication with a master device. An additional level shifter circuit at the SDA data IO and SCL clock input is integrated which makes it independent of the interface voltage levels of the master device. This circuit also isolates the slave device and protects it from high voltage spikes from master. The controller is designed with finite state machine (FSM) model in a synchronous fashion. The design is integrated in a pressure sensor for chip calibration and register configuration and it is fabricated with 180 nm CMOS technology. The I2CSSC occupies a very small area of 5712 μm2 and it requires only 650 gates for its implementation. The current consumption is upto 87 μΑ from 1.8 V power supply and it needs only 157 μ' power for its full operation. The measurement results verify the functional accuracy and rigorousness of the proposed design with all I2C operating modes.