Gyusub Won, Dongsoo Lee, SungHun Cho, Kangyoon Lee
{"title":"具有电阻反馈的d类CMOS功率放大器的设计","authors":"Gyusub Won, Dongsoo Lee, SungHun Cho, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368816","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a power amplifier with improved Efficiency and compact structure by using Resistor Feedback Technique. CMOS Class-D Type Power Amplifier with wide output range is presented. The proposed design is implemented in 55 nm 1P6M CMOS process. The measured maximum output power of PA is 10 dBm with a PAE of 25.8 % from a 3-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of power-efficient class-D CMOS power amplifier with resistor feedback\",\"authors\":\"Gyusub Won, Dongsoo Lee, SungHun Cho, Kangyoon Lee\",\"doi\":\"10.1109/ISOCC.2017.8368816\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a power amplifier with improved Efficiency and compact structure by using Resistor Feedback Technique. CMOS Class-D Type Power Amplifier with wide output range is presented. The proposed design is implemented in 55 nm 1P6M CMOS process. The measured maximum output power of PA is 10 dBm with a PAE of 25.8 % from a 3-V supply.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368816\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368816","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of power-efficient class-D CMOS power amplifier with resistor feedback
In this paper, we propose a power amplifier with improved Efficiency and compact structure by using Resistor Feedback Technique. CMOS Class-D Type Power Amplifier with wide output range is presented. The proposed design is implemented in 55 nm 1P6M CMOS process. The measured maximum output power of PA is 10 dBm with a PAE of 25.8 % from a 3-V supply.