{"title":"一个四分之一速率的3分接DFE,用于4Gbps数据速率,基于第一个推测分接的开关容量","authors":"Gyunam Jeon, Yong-Bin Kim","doi":"10.1109/ISOCC.2017.8368875","DOIUrl":null,"url":null,"abstract":"This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap\",\"authors\":\"Gyunam Jeon, Yong-Bin Kim\",\"doi\":\"10.1109/ISOCC.2017.8368875\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368875\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap
This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.