{"title":"用于纳米瓦CMOS lsi的1.2 V, 33 ppm/°C, 40 nW，基于再生的BGR电路","authors":"Abhishek Shrivastava, Amandeep Kaur, M. Sarkar","doi":"10.1109/ISOCC.2017.8368794","DOIUrl":null,"url":null,"abstract":"A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C–90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is −47 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs\",\"authors\":\"Abhishek Shrivastava, Amandeep Kaur, M. Sarkar\",\"doi\":\"10.1109/ISOCC.2017.8368794\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C–90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is −47 dB.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368794\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs
A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C–90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is −47 dB.
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