Deeksha Verma, Hye-Yeong Kang, Khuram Shehzad, M. R. Rehman, Kangyoon Lee
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Design of asynchronous SAR ADC for low power mixed signal applications
This paper presents a 10-bit, 8 MS/s Asynchronous SAR ADC with supply voltages of 1 V for low power mixed signal applications. The proposed asynchronous ADC consist of a comparator, SAR logic block and two control blocks (positive CDAC and Negative CDAC). The prototype of the proposed Asynchronous SAR ADC is implemented in 55 nm CMOS process technology. It achieves ENOB of 9.765 bit with sampling frequency of 8MS/s, input range of 0.2–0.8 V and power consumption is 0.124 mW.
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