Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kangyoon Lee
{"title":"基于混合控制技术的高效数字PWMDC-DC变换器","authors":"Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368853","DOIUrl":null,"url":null,"abstract":"We have proposed a DC-DC Converter with high efficiency for ultra-low power Energy Harvesting (EH) applications. To achieve the high efficiency while remaining the high accuracy, the control signal pulse width is generated digitally instead of analog as in the conventional DC-DC converter. The presented Digital Pulse Width Modulation (DPWM) DC-DC converter employs the hybrid control technique which consists of the counter based and the open delay locked loop based topology. The output range of this converter can be from 4.5V to 6V by using 3-bits control with the trimming step of 20 mV. The power conversion efficiency of the proposed converter is 93% at 500mA load. Our proposed buck DC-DC converter is realized with CMOS 0.18 μm technology with the die size of 1200 μm × 980 μm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications\",\"authors\":\"Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kangyoon Lee\",\"doi\":\"10.1109/ISOCC.2017.8368853\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have proposed a DC-DC Converter with high efficiency for ultra-low power Energy Harvesting (EH) applications. To achieve the high efficiency while remaining the high accuracy, the control signal pulse width is generated digitally instead of analog as in the conventional DC-DC converter. The presented Digital Pulse Width Modulation (DPWM) DC-DC converter employs the hybrid control technique which consists of the counter based and the open delay locked loop based topology. The output range of this converter can be from 4.5V to 6V by using 3-bits control with the trimming step of 20 mV. The power conversion efficiency of the proposed converter is 93% at 500mA load. Our proposed buck DC-DC converter is realized with CMOS 0.18 μm technology with the die size of 1200 μm × 980 μm.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"1 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368853\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications
We have proposed a DC-DC Converter with high efficiency for ultra-low power Energy Harvesting (EH) applications. To achieve the high efficiency while remaining the high accuracy, the control signal pulse width is generated digitally instead of analog as in the conventional DC-DC converter. The presented Digital Pulse Width Modulation (DPWM) DC-DC converter employs the hybrid control technique which consists of the counter based and the open delay locked loop based topology. The output range of this converter can be from 4.5V to 6V by using 3-bits control with the trimming step of 20 mV. The power conversion efficiency of the proposed converter is 93% at 500mA load. Our proposed buck DC-DC converter is realized with CMOS 0.18 μm technology with the die size of 1200 μm × 980 μm.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
