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2017 International SoC Design Conference (ISOCC)最新文献

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A multiband fully integrated high-linearity power amplifier using a 0.18-μm CMOS process for LTE applications 采用0.18 μm CMOS工艺的多频带全集成高线性功率放大器，适用于LTE应用
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368814
Tsung-Ying Wu, Jeng-Rern Yang
{"title":"A multiband fully integrated high-linearity power amplifier using a 0.18-μm CMOS process for LTE applications","authors":"Tsung-Ying Wu, Jeng-Rern Yang","doi":"10.1109/ISOCC.2017.8368814","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368814","url":null,"abstract":"This paper presents a multiband high-linearity power amplifier (PA) for long-term evolution (LTE) applications at 1.8/2.1/2.3/2.5/2.6 GHz in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm 1P6M CMOS process. The proposed PA includes a switch, which is a CMOS varactor, a driver stage, which is a CMOS resistor inverter, and a power stage, which uses a cascode structure and feedback technique. The fully integrated PA delivers 21-dBm output power in the overall band for a 50-Ω load with an average power gain of 22.98 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117230907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hardware feasible offset and gain error correction for time-interleaved ADC 时间交错ADC的硬件可行偏移和增益误差校正
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368881
Sadeque Reza Khan, A. Ferdousi, Goangseog Choi
{"title":"Hardware feasible offset and gain error correction for time-interleaved ADC","authors":"Sadeque Reza Khan, A. Ferdousi, Goangseog Choi","doi":"10.1109/ISOCC.2017.8368881","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368881","url":null,"abstract":"An entirely digital method of TIADC error calibration is presented in this paper. The methodology is based on statistical properties of signals for error estimations particularly targeting mean and variance of samples. In the proposed algorithm offset mismatch can be corrected by subtracting the estimated offset from each sub-ADC digital samples. Similarly, gain mismatch can be corrected by multiplying the output of each sub-ADC by the inverse of its estimated gain and both of these corrections, offset and gain, are cost effective in terms of hardware.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114247047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wireless low power toxic gas detector based on ADuCM360 基于ADuCM360的无线低功耗有毒气体检测仪
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368836
Minming Gu, Zhenping Xia, Yan Lei, Lin Zhang, Jieming Ma
{"title":"Wireless low power toxic gas detector based on ADuCM360","authors":"Minming Gu, Zhenping Xia, Yan Lei, Lin Zhang, Jieming Ma","doi":"10.1109/ISOCC.2017.8368836","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368836","url":null,"abstract":"In order to avoid toxic gas poisoning incident, explosion and improve people's quality of life, this project designed the wireless low power toxic gas detector based on ADuCM360 with sensor technology and wireless transmission technology. The system consists of power management module, sensor module, signal conditioning module and wireless communication module. Analysis and experimental results show that this toxic gas detector can monitor and store the toxic gas concentration, temperature and humidity in the room for a long time. You will be able to understand the detection of toxic gases without necessity of visiting the site in person.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS 65纳米CMOS有源并联反馈无电感低噪声放大器的设计方法
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368778
Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Makoto Nakamura
{"title":"Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS","authors":"Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Makoto Nakamura","doi":"10.1109/ISOCC.2017.8368778","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368778","url":null,"abstract":"We propose a design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS and analyze the characteristics. The gain of the NMOS should be larger than that of the PMOS for improvement of the voltage gain and the noise figure. A bandwidth of around 8 GHz was obtained in an analysis using a circuit simulation of the designed low-noise amplifier, which is higher than that of the conventional 0.13 μm CMOS type.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124190757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer 6并联射频能量收集整流器，具有高功率转换效率(PCE)，用于5.8GHz 3W无线电力传输
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368855
Zaffar Hayat Nawaz Khan, Danial Khan, Nabeel Ahmad, Hamed Abbasizadeh, Syed Asmat Ali Shah, Young Jun Park, Kangyoon Lee
{"title":"6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer","authors":"Zaffar Hayat Nawaz Khan, Danial Khan, Nabeel Ahmad, Hamed Abbasizadeh, Syed Asmat Ali Shah, Young Jun Park, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368855","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368855","url":null,"abstract":"This paper presents a 6-parallel RF-DC Energy Harvesting (EH) Rectifier with Dickson Charge Pump Structure. The 6-parallel RF-DC EH Rectifier is used and receives a total power of 3W, 500mW by each stage. This parallel structure reduces the voltage that the devices must withstand to avoid limiting their operation due to device characteristics. Proposed RF EH Rectifier is designed with an 180nm BCD process and achieves maximum power conversion efficiency (PCE) of 85.51 percent at 3W input power while delivering an output DC voltage of 11.32V to 50-ohm load resistance.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121925601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications 低功耗10位SAR ADC，采用ab类放大器，用于物联网应用
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368864
Khuram Shehzad, Hye-Young Kang, Deeksha Verma, Young Jun Park, Kangyoon Lee
{"title":"Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications","authors":"Khuram Shehzad, Hye-Young Kang, Deeksha Verma, Young Jun Park, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368864","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368864","url":null,"abstract":"In this paper, we present a low-power 10 Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) which is suitable for low power mixed signal applications especially for IoT devices. We have used Class-AB type amplifier in Reference generator of SAR ADC to reduce current consumption and to satisfy the linearity property for better performance of ADC. The proposed circuit uses a CMOS 0.18 μm process technology and supply voltage of 5 V. The ENOB is 9.623 Bit and SNDR of 58.688 dB with current consumption of 0.44 mA.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications 用于BLE应用的2.4 ghz 2.2 mw CMOS射频接收器前端设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368815
Shinil Chang, Yongho Lee, Hyunchol Shin
{"title":"Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications","authors":"Shinil Chang, Yongho Lee, Hyunchol Shin","doi":"10.1109/ISOCC.2017.8368815","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368815","url":null,"abstract":"A sliding-IF RF receiver front-end is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low power consumption, the receiver front-end circuits are designed with a 1-V supply voltage. Simulations show that the receiver has a 55.5 dB full-path maximum gain, and −43.5 dBm input-referred P1dB while dissipating only 2.2 mW. At the maximum gain, the noise figure is 3.2 dB, which corresponds to the sensitivity of −98.8 dBm when the minimum required SNR of a demodulator is 12 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.5-V 320 μW CMOS MedRadio receiver RF front-end with a current-reuse gw-boosting common gate low noise amplifier 一种0.5 v 320 μW CMOS MedRadio接收机射频前端，带有电流复用gw升压共门低噪声放大器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368872
Taejong Kim, Sinyoung Kim, K. Kwon
{"title":"A 0.5-V 320 μW CMOS MedRadio receiver RF front-end with a current-reuse gw-boosting common gate low noise amplifier","authors":"Taejong Kim, Sinyoung Kim, K. Kwon","doi":"10.1109/ISOCC.2017.8368872","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368872","url":null,"abstract":"In this paper, an ultra-low-power medical device radiocommunications service (MedRadio) receiver RF front-end employing a current-reuse gm-boosting common-gate low noise amplifier (CGLNA) is proposed. The proposed current-reuse gm-boosting CGLNA has larger voltage gain and lower NF characteristics than a conventional gm-boosting CGLNA with the same power consumption. The RF front-end, implemented in a 0.13 μm CMOS process, consumes 320 μ W from a 0.5-V supply voltage. It achieves a conversion gain of 37 dB, NF of 3.4 dB, S11 of less than −10 dB, and an IIP3 of −34 dBm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131490878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of a reduction algorithm for CAN frame bits CAN帧位约简算法的开发
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368802
Ronnie Opone Serfa Juan, Byoung Hwan Ko, Chan Su Park, Hi-Seok Kim
{"title":"Development of a reduction algorithm for CAN frame bits","authors":"Ronnie Opone Serfa Juan, Byoung Hwan Ko, Chan Su Park, Hi-Seok Kim","doi":"10.1109/ISOCC.2017.8368802","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368802","url":null,"abstract":"Controller Area Network (CAN) protocol uses Cyclic Redundancy Check (CRC) code as a self-correcting scheme to detect and correct errors. Also, the assigned CRC generator polynomial for CAN is CRC-15. Therefore, no matter what is the size of the data frame to transmit, it already consumed 15 bits for CRC frame that causes to decrease the CAN's frame rate. The main objective of this paper is to use a different error correction technique which is called as the Enhanced-Error Detection (EED) code and aims to increase the CAN's frame rate. The computed redundancy bits depends on the total number of transmitted bits instead of a fixed set of bits. Moreover, these redundancy bits will be placed right after of the data bits' position like in CRC scheme. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results show a significant increase of CAN's frame rate and can be a better option for detecting and correcting the error in CAN System.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131826410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Time-domain temperature sensor based on interlaced hysteresis delay cells 基于交错迟滞延迟单元的时域温度传感器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368896
Y. Hong, Yong-Bin Kim, Kyung Ki Kim
{"title":"Time-domain temperature sensor based on interlaced hysteresis delay cells","authors":"Y. Hong, Yong-Bin Kim, Kyung Ki Kim","doi":"10.1109/ISOCC.2017.8368896","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368896","url":null,"abstract":"This paper presents a low power and small area temperature sensor with interlaced hysteresis delay cells (IHDCs) instead of using inverter-based buffers. IHDC consumes lower power and occupies smaller silicon area than inverter-based buffers. A pulse width which is proportionate to temperature is produced by the proposed temperature-to-pulse generator. Two different delay lines and an XOR gate are employed to detect pulse width for temperature measurement. Temperature dependent and thermal insensitive delay lines are used as the two different delay lines. The output of the temperature-to-pulse generator is converted to digital output by a time-to-digital converter. This temperature sensor is simulated with 0.18um CMOS technology and 1.8V supply voltage, and it shows a good linearity with lower power consumption compared to conventional ones. The proposed temperature sensor consumes 1.185 mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129949565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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