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2017 International SoC Design Conference (ISOCC)最新文献

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Dynamic power estimation for ROM-less DDFS designs using switching activity analysis 基于开关活动分析的无rom DDFS动态功率估计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368895
Wei Wang, Yuanzi Xu, Chua-Chin Wang
{"title":"Dynamic power estimation for ROM-less DDFS designs using switching activity analysis","authors":"Wei Wang, Yuanzi Xu, Chua-Chin Wang","doi":"10.1109/ISOCC.2017.8368895","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368895","url":null,"abstract":"A pre-realization dynamic power estimation approach for ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, which carries out the analysis of switching activity of all the major logic blocks utilized in the synthesis of ROM-less DDFS. As soon as the partitions of the π/2 and the characteristic equations for polynomial interpolation are given, the proposed approach is able to assess the overall switching activities such that the power profile of different combination of partitions and equations can be derived before any physical implementation.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface 基于训练数据模式的8Gb/s自适应DFE移动DRAM接口电平校准
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368898
Minchang Kim, Jihwan Park, Joo-Hyung Chae, H. Ko, Mino Kim, Suhwan Kim
{"title":"An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface","authors":"Minchang Kim, Jihwan Park, Joo-Hyung Chae, H. Ko, Mino Kim, Suhwan Kim","doi":"10.1109/ISOCC.2017.8368898","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368898","url":null,"abstract":"An 8Gb/s adaptive decision feedback equalizer (DFE) using training sequence is designed in a 65nm CMOS. The training data pattern ‘10111111’ is used to detect distorted data level periodically. The tap coefficients are automatically adjusted during the training mode by compensating for the difference between the distorted data level and ideal high DC level. The power consumption is 10.4mW at 1.05V supply voltage and the adaptation time is 90ns. The simulation results show the improvement of data eye after training the tap coefficients. The data eye width and height are improved from 0.36UI to 0.84UI and from 40mV to 90mV, respectively.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130683246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power relaxation oscillator with improved thermal stability 提高热稳定性的低功耗弛豫振荡器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368796
L. Peng, Yuan Cao, Xiaofang Pan, Xiaojin Zhao
{"title":"A low-power relaxation oscillator with improved thermal stability","authors":"L. Peng, Yuan Cao, Xiaofang Pan, Xiaojin Zhao","doi":"10.1109/ISOCC.2017.8368796","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368796","url":null,"abstract":"In this paper, we present a novel on-chip relaxation oscillator (RO) with high temperature stability. By employing delay compensation circuit (DCC) in the delay loop, the transmission delay, which is highly sensitive to the temperature variation, is well-suppressed, leading to significantly elevated temperature stability of the RO's period. In addition, the proposed RO implementation features a low power consumption of 0.11μW at 25° C, using 65nm 1.2V standard CMOS process. Moreover, according to our extensive simulation results, the variation of our proposed RO's output frequency is reduced to ±0.18% with the working temperature ranged from −55° C to 125° C, outperforming the other state of art RO designs.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131212448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Embedded system-on-chip design of atrial fibrillation classifier 房颤分类器的嵌入式片上系统设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368784
Huey Woan Lim, Y. Hau, M. A. Othman, Chiao Wen Lim
{"title":"Embedded system-on-chip design of atrial fibrillation classifier","authors":"Huey Woan Lim, Y. Hau, M. A. Othman, Chiao Wen Lim","doi":"10.1109/ISOCC.2017.8368784","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368784","url":null,"abstract":"Atrial Fibrillation (AFIB) is one of the major risk factors of stroke and heart failure which can be observed from the electrocardiogram (ECG). This paper presents an embedded system-on-chip (SoC) architecture design of AFIB detection based on stationary wavelet transform (SWT) and artificial neural network (ANN) algorithm for heart screening propose. The architecture is designed using the hardware/software co-design technique and prototyped on Altera DE2-115 FPGA platform. Hardware acceleration of compute intensive FFT operation is also carried out to enhance computation timing performance. The whole system consumes 40,830 LEs of Altera Cyclone-IV FPGA device. The total computation time of AFIB classifier is 22 seconds for 10 seconds ECG input data with the accuracy of 95.3% which able to detect AFIB rhythm, normal sinus rhythm, and non-AFIB rhythm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134331936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A study of low jitter phase locked loop for SPDIF SPDIF低抖动锁相环的研究
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368891
Jihoon Kim, Yong Moon
{"title":"A study of low jitter phase locked loop for SPDIF","authors":"Jihoon Kim, Yong Moon","doi":"10.1109/ISOCC.2017.8368891","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368891","url":null,"abstract":"CDR (Clock data recovery) circuit is an essential component for serial data communication. S/PDIF generates a lot of jitter from 2T and 3T. The PLL recognizes that the frequency changes in 2T and 3T portion. Change in frequency loses locking of the block. 3T detector reset Circuit is designed for reducing the jitter. Output jitter specifications of 9 frequencies are satisfied. 65nm CMOS process is used in this study.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130014022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high-speed, low-offset and low-power differential comparator for analog to digital converters 一种用于模数转换器的高速、低偏置和低功率差分比较器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368862
Mehdi Nasrollahpour, Chin-Hsien Yen, S. Hamedi-Hagh
{"title":"A high-speed, low-offset and low-power differential comparator for analog to digital converters","authors":"Mehdi Nasrollahpour, Chin-Hsien Yen, S. Hamedi-Hagh","doi":"10.1109/ISOCC.2017.8368862","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368862","url":null,"abstract":"Analysis and design of a high-speed comparator with improved input referred offset is presented in this paper. The proposed comparator is designed in TSMC low power CMOS technology under 1.2 V power supply. The new presented comparator has a low power consumption and utilizes dual offset cancellation technique. The minimum convertible input voltage is calculated to be 52 μV and the propagation delay at this worst case is equal to 219 ps. The power consumption at 1 GHz clock frequency is 755 μW. Monte Carlo simulation with 500 points iteration shows that the standard deviation of the input referred offset is about 723 μV.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Scalable deep neural network accelerator cores with cubic integration using through chip interface 可扩展的深度神经网络加速器核心与立方集成使用通过芯片接口
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368843
Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, T. Ohkubo, Takuya Kojima, H. Amano
{"title":"Scalable deep neural network accelerator cores with cubic integration using through chip interface","authors":"Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, T. Ohkubo, Takuya Kojima, H. Amano","doi":"10.1109/ISOCC.2017.8368843","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368843","url":null,"abstract":"Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133888244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1 MHz–10.2 MHz BW/0 dB–70 dB gain DPOTA-based baseband chain receiver 1 MHz - 10.2 MHz BW/0 dB - 70 dB增益基于dpota的基带链式接收机
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368798
M. B. Elamien, S. Mahmoud
{"title":"A 1 MHz–10.2 MHz BW/0 dB–70 dB gain DPOTA-based baseband chain receiver","authors":"M. B. Elamien, S. Mahmoud","doi":"10.1109/ISOCC.2017.8368798","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368798","url":null,"abstract":"In this paper, a digital programmable OTA-based multi-standard receiver analog baseband (ABB) chain is proposed. The proposed ABB consists of a 4th-order Butterworth low-pass filter (LPF) and two programmable gain amplifiers (PGAs). The LPF exhibits a cutoff frequency tuning range from 1 MHz to 10.2 MHz, thus, it covers Bluetooth, UMTS, DVB-H and IEEE 802.11a/g standards. The gain of the proposed PGA varies from 0 dB to 35 dB with a step of 5 dB. The ABB is designed and simulated in 90 nm CMOS technology with a balanced 1.2 V supply voltage. The IIP3 of the proposed ABB is 23.9 dBm and the overall power consumption is 9.1 mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"108 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133171071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterizing convolutional neural network workloads on a detailed GPU simulator 在详细的GPU模拟器上表征卷积神经网络工作负载
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368781
Kwanghee Chang, Minsik Kim, Kyungah Kim, W. Ro
{"title":"Characterizing convolutional neural network workloads on a detailed GPU simulator","authors":"Kwanghee Chang, Minsik Kim, Kyungah Kim, W. Ro","doi":"10.1109/ISOCC.2017.8368781","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368781","url":null,"abstract":"Recent frameworks on convolutional neural networks (CNNs) such as Caffe and MXNet have focused primarily on being compatible with CUDA software and hardware application. However, it was designed for GPU architecture of compute capability 3.0 and above. Therefore, it needs verification of function to perform GPGPU-Sim which is implemented as NVIDIA compute capability devices 2.x. We developed a framework which can make inferencing AlexNet on GPGPU-Sim. We also analyze the execution results of the GPGPU-Sim. The number of lines in one set of the L1 data cache is sensitive to influence performance of AlexNet inference.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.6mW 320×240 pixel vision sensor for event detection 用于事件检测的1.6mW 320×240像素视觉传感器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368787
Yu Zou, M. Gottardi, M. Lecca
{"title":"A 1.6mW 320×240 pixel vision sensor for event detection","authors":"Yu Zou, M. Gottardi, M. Lecca","doi":"10.1109/ISOCC.2017.8368787","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368787","url":null,"abstract":"This paper reports on a low-power vision sensor embedding a custom algorithm for event detection. Anomalous or suspicious motions occurring in the scene are isolated from the background by continuously monitoring the time variation of the pixel intensity with respect to two thresholds that are dynamically updated. Pixels whose intensity is out of the range defined by these thresholds are considered as a part of a possibly anomalous activity and they are called hot pixels. The sensor has been fabricated in a 110nm CMOS technology. It delivers grayscale images in QVGA format and related hot-pixel bitmaps at 15 fps with a power consumption of 1.6mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121969491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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