Dynamic power estimation for ROM-less DDFS designs using switching activity analysis

Abstract

A pre-realization dynamic power estimation approach for ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, which carries out the analysis of switching activity of all the major logic blocks utilized in the synthesis of ROM-less DDFS. As soon as the partitions of the π/2 and the characteristic equations for polynomial interpolation are given, the proposed approach is able to assess the overall switching activities such that the power profile of different combination of partitions and equations can be derived before any physical implementation.