SPDIF低抖动锁相环的研究

2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI:10.1109/ISOCC.2017.8368891

Jihoon Kim, Yong Moon

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引用次数: 0

摘要

时钟数据恢复(CDR)电路是串行数据通信的重要组成部分。S/PDIF从2T和3T产生很多抖动。锁相环识别2T和3T部分的频率变化。频率的改变使块失去锁定。3T探测器复位电路的设计是为了减少抖动。满足9个频率的输出抖动指标。本研究采用65nm CMOS工艺。

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A study of low jitter phase locked loop for SPDIF

CDR (Clock data recovery) circuit is an essential component for serial data communication. S/PDIF generates a lot of jitter from 2T and 3T. The PLL recognizes that the frequency changes in 2T and 3T portion. Change in frequency loses locking of the block. 3T detector reset Circuit is designed for reducing the jitter. Output jitter specifications of 9 frequencies are satisfied. 65nm CMOS process is used in this study.

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2017 International SoC Design Conference (ISOCC)

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