65纳米CMOS有源并联反馈无电感低噪声放大器的设计方法

2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI:10.1109/ISOCC.2017.8368778

Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Makoto Nakamura

{"title":"65纳米CMOS有源并联反馈无电感低噪声放大器的设计方法","authors":"Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Makoto Nakamura","doi":"10.1109/ISOCC.2017.8368778","DOIUrl":null,"url":null,"abstract":"We propose a design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS and analyze the characteristics. The gain of the NMOS should be larger than that of the PMOS for improvement of the voltage gain and the noise figure. A bandwidth of around 8 GHz was obtained in an analysis using a circuit simulation of the designed low-noise amplifier, which is higher than that of the conventional 0.13 μm CMOS type.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS\",\"authors\":\"Toshiyuki Inoue, A. Tsuchiya, K. Kishine, Makoto Nakamura\",\"doi\":\"10.1109/ISOCC.2017.8368778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS and analyze the characteristics. The gain of the NMOS should be larger than that of the PMOS for improvement of the voltage gain and the noise figure. A bandwidth of around 8 GHz was obtained in an analysis using a circuit simulation of the designed low-noise amplifier, which is higher than that of the conventional 0.13 μm CMOS type.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种65纳米有源并联反馈无电感低噪声放大器的设计方法，并对其特性进行了分析。NMOS的增益应大于PMOS的增益，以改善电压增益和噪声系数。通过电路仿真分析，所设计的低噪声放大器的带宽约为8 GHz，高于传统0.13 μm CMOS放大器的带宽。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS

We propose a design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS and analyze the characteristics. The gain of the NMOS should be larger than that of the PMOS for improvement of the voltage gain and the noise figure. A bandwidth of around 8 GHz was obtained in an analysis using a circuit simulation of the designed low-noise amplifier, which is higher than that of the conventional 0.13 μm CMOS type.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 International SoC Design Conference (ISOCC)

自引率

0.00%

发文量