{"title":"时间交错ADC的硬件可行偏移和增益误差校正","authors":"Sadeque Reza Khan, A. Ferdousi, Goangseog Choi","doi":"10.1109/ISOCC.2017.8368881","DOIUrl":null,"url":null,"abstract":"An entirely digital method of TIADC error calibration is presented in this paper. The methodology is based on statistical properties of signals for error estimations particularly targeting mean and variance of samples. In the proposed algorithm offset mismatch can be corrected by subtracting the estimated offset from each sub-ADC digital samples. Similarly, gain mismatch can be corrected by multiplying the output of each sub-ADC by the inverse of its estimated gain and both of these corrections, offset and gain, are cost effective in terms of hardware.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Hardware feasible offset and gain error correction for time-interleaved ADC\",\"authors\":\"Sadeque Reza Khan, A. Ferdousi, Goangseog Choi\",\"doi\":\"10.1109/ISOCC.2017.8368881\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An entirely digital method of TIADC error calibration is presented in this paper. The methodology is based on statistical properties of signals for error estimations particularly targeting mean and variance of samples. In the proposed algorithm offset mismatch can be corrected by subtracting the estimated offset from each sub-ADC digital samples. Similarly, gain mismatch can be corrected by multiplying the output of each sub-ADC by the inverse of its estimated gain and both of these corrections, offset and gain, are cost effective in terms of hardware.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368881\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368881","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware feasible offset and gain error correction for time-interleaved ADC
An entirely digital method of TIADC error calibration is presented in this paper. The methodology is based on statistical properties of signals for error estimations particularly targeting mean and variance of samples. In the proposed algorithm offset mismatch can be corrected by subtracting the estimated offset from each sub-ADC digital samples. Similarly, gain mismatch can be corrected by multiplying the output of each sub-ADC by the inverse of its estimated gain and both of these corrections, offset and gain, are cost effective in terms of hardware.