{"title":"用于BLE应用的2.4 ghz 2.2 mw CMOS射频接收器前端设计","authors":"Shinil Chang, Yongho Lee, Hyunchol Shin","doi":"10.1109/ISOCC.2017.8368815","DOIUrl":null,"url":null,"abstract":"A sliding-IF RF receiver front-end is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low power consumption, the receiver front-end circuits are designed with a 1-V supply voltage. Simulations show that the receiver has a 55.5 dB full-path maximum gain, and −43.5 dBm input-referred P1dB while dissipating only 2.2 mW. At the maximum gain, the noise figure is 3.2 dB, which corresponds to the sensitivity of −98.8 dBm when the minimum required SNR of a demodulator is 12 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications\",\"authors\":\"Shinil Chang, Yongho Lee, Hyunchol Shin\",\"doi\":\"10.1109/ISOCC.2017.8368815\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A sliding-IF RF receiver front-end is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low power consumption, the receiver front-end circuits are designed with a 1-V supply voltage. Simulations show that the receiver has a 55.5 dB full-path maximum gain, and −43.5 dBm input-referred P1dB while dissipating only 2.2 mW. At the maximum gain, the noise figure is 3.2 dB, which corresponds to the sensitivity of −98.8 dBm when the minimum required SNR of a demodulator is 12 dB.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368815\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368815","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications
A sliding-IF RF receiver front-end is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low power consumption, the receiver front-end circuits are designed with a 1-V supply voltage. Simulations show that the receiver has a 55.5 dB full-path maximum gain, and −43.5 dBm input-referred P1dB while dissipating only 2.2 mW. At the maximum gain, the noise figure is 3.2 dB, which corresponds to the sensitivity of −98.8 dBm when the minimum required SNR of a demodulator is 12 dB.
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