A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver

A 2.56 GSymbol/s receiver including clock recovery circuit is proposed for the mobile industry processor interface (MIPI) C-PHY version 1.0. The clock recovery circuit using a dynamic logic generates a clock signal sensing at least one transition among three received data. Furthermore, it removes a glitch noise generated due to the delay mismatch of three high-speed receivers using a deglitch circuit. The proposed C-PHY receiver including clock recovery circuit is implemented using a 0.11-μm CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the recovered clock is approximately 17.5 ps at a date rate of 2.56 GSymbol/s.