发布求助
文献互助 智能选刊 最新文献

2006 15th Asian Test Symposium最新文献

筛选
英文 中文
A Digital BIST Methodology for Spread Spectrum Clock Generators 扩频时钟发生器的数字BIST方法
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.8
Maohsuan Chou, Jen-Chien Hsu, C. Su
{"title":"A Digital BIST Methodology for Spread Spectrum Clock Generators","authors":"Maohsuan Chou, Jen-Chien Hsu, C. Su","doi":"10.1109/ATS.2006.8","DOIUrl":"https://doi.org/10.1109/ATS.2006.8","url":null,"abstract":"In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
At-Speed Testing with Timing Exceptions and Constraints-Case Studies 带时间异常和约束的高速测试——案例研究
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.26
Dhiraj Goswami, Kun-Han Tsai, M. Kassab, Takeo Kobayashi, J. Rajski, B. Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, T. Aikyo
{"title":"At-Speed Testing with Timing Exceptions and Constraints-Case Studies","authors":"Dhiraj Goswami, Kun-Han Tsai, M. Kassab, Takeo Kobayashi, J. Rajski, B. Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, T. Aikyo","doi":"10.1109/ATS.2006.26","DOIUrl":"https://doi.org/10.1109/ATS.2006.26","url":null,"abstract":"In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121153169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains 基于动态因子使用定义链的可观察分支覆盖度量
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.24
Tao Lv, Ling-Yi Liu, Yang Zhao, Hua-wei Li, Xiao-wei Li
{"title":"An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains","authors":"Tao Lv, Ling-Yi Liu, Yang Zhao, Hua-wei Li, Xiao-wei Li","doi":"10.1109/ATS.2006.24","DOIUrl":"https://doi.org/10.1109/ATS.2006.24","url":null,"abstract":"In this paper we propose an observability branch coverage metric (OBCM) based on dynamic factored use-define chains, along with its evaluation method. This technique exploits the efficiency of data-flow analysis rather than methods like fault simulation. Hence it can be easily integrated into HDL compilers or simulators. Experimental results show that OBCM can provide more meaningful coverage data for functional verification than traditional branch coverage metric (BCM)","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132034056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design for Testability of Software-Based Self-Test for Processors 基于软件的处理器自检可测试性设计
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.38
Masato Nakazato, S. Ohtake, M. Inoue, H. Fujiwara
{"title":"Design for Testability of Software-Based Self-Test for Processors","authors":"Masato Nakazato, S. Ohtake, M. Inoue, H. Fujiwara","doi":"10.1109/ATS.2006.38","DOIUrl":"https://doi.org/10.1109/ATS.2006.38","url":null,"abstract":"In this paper, the authors propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design, and it enables at-speed testing and does not induce delay overhead","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127056876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A Functional Fault Model with Implicit Fault Effect Propagation Requirements 具有隐式故障效应传播需求的功能故障模型
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.10
I. Pomeranz, S. Patil, Praveen Parvathala
{"title":"A Functional Fault Model with Implicit Fault Effect Propagation Requirements","authors":"I. Pomeranz, S. Patil, Praveen Parvathala","doi":"10.1109/ATS.2006.10","DOIUrl":"https://doi.org/10.1109/ATS.2006.10","url":null,"abstract":"We define a functional fault model that does not include explicit fault effect propagation requirements. Test generation for this functional fault model is done considering only a fault free circuit. This simplifies the functional test generation process. We demonstrate through experimental results that functional test sequences generated based on this model are effective in providing very high gate-level stuck-at fault coverage","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage 倾斜负载转换测试覆盖的布局感知扫描链重排
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.57
Sying-Jyan Wang, K. Peng, Katherine Shu-Min Li
{"title":"Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage","authors":"Sying-Jyan Wang, K. Peng, Katherine Shu-Min Li","doi":"10.1109/ATS.2006.57","DOIUrl":"https://doi.org/10.1109/ATS.2006.57","url":null,"abstract":"In this paper, we propose a layout-based scan chain ordering method to improve fault coverage for skewed-load delay test with minimum routing overhead. This approach provides many advantages over previous methods. (1) The proposed method can provide 100% test pair coverage for all detectable transition faults. (2) With layout information taken into account, the routing penalty is small, and thus the impact on circuit performance is not significant","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115208727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Histogram Based Testing Strategy for ADC 基于直方图的ADC测试策略
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.52
Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang
{"title":"Histogram Based Testing Strategy for ADC","authors":"Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang","doi":"10.1109/ATS.2006.52","DOIUrl":"https://doi.org/10.1109/ATS.2006.52","url":null,"abstract":"An improved histogram testing method for analog-to-digital converters (ADCs) is proposed. The proposed method reveals not only the static performance but also the dynamic ones, such as the effective number of bits (ENOB) with a sinusoidal input signal. Therefore, single histogram testing is performed rather than using both the histogram and spectral methods to reduce the total test cost. The proposed testing method was experimentally validated on a commercial 8-bit ADC to demonstrate it effectiveness. The experimental result indicated that the proposed histogram-based test method exhibits a good agreement to the measured results of the classical FFT-based method","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125522269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An Application of IDD Spectrum Testing Method to the Fault Analysis IDD频谱测试方法在故障分析中的应用
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.19
K. Sakaguchi
{"title":"An Application of IDD Spectrum Testing Method to the Fault Analysis","authors":"K. Sakaguchi","doi":"10.1109/ATS.2006.19","DOIUrl":"https://doi.org/10.1109/ATS.2006.19","url":null,"abstract":"IDDQ information is very useful to localize faults in a LSI. But it is time consuming to discover test vectors which induce abnormal IDDQ. Since the IDD spectrum testing method can detect abnormal supply current easily, we can acquire the test vector information in a short time by the method. An application of the method is introduced and we show experimental results","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126516079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Plug once, test everything 插一次，测试一切
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.65
A. S. Yawelak, C. Viho
{"title":"Plug once, test everything","authors":"A. S. Yawelak, C. Viho","doi":"10.1109/ATS.2006.65","DOIUrl":"https://doi.org/10.1109/ATS.2006.65","url":null,"abstract":"Configuration management presents several challenges to test suite execution in interoperability testing. Several nodes have to be rearranged from test to test in a reliable and efficient way. This work proposes a novel methodology based on the replacement of underlying networking technologies to transparently automate the process. The methodology is presented and initial results are exposed","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126920127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction 面向测试数据和测试时间的可感知扫描链路由多模式分段扫描体系结构
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1049/iet-cdt:20070115
Po-Chang Tsai, Sying-Jyan Wang
{"title":"Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction","authors":"Po-Chang Tsai, Sying-Jyan Wang","doi":"10.1049/iet-cdt:20070115","DOIUrl":"https://doi.org/10.1049/iet-cdt:20070115","url":null,"abstract":"This paper presents multi-mode segmented scan architecture. Three operation modes are supported: broadcast, multicast, and serial. Efficient test data compression can be achieved under this architecture with limited hardware overhead. An efficient two-way partitioning algorithm is given to construct multicast-mode configurations. Finally, we present a layout-aware scan chain routing for test compaction, which has not yet explored by the researchers. Experimental results show that most of the serial scan operations can be replaced by multicast operations, and thus achieve much better compression rate","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125242187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信