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2006 15th Asian Test Symposium最新文献

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A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops 支持多嵌套循环算法的现场可编程存储器BIST体系结构
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.9
Xiaogang Du, N. Mukherjee, Chris Hill, Wu-Tung Cheng, S. Reddy
{"title":"A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops","authors":"Xiaogang Du, N. Mukherjee, Chris Hill, Wu-Tung Cheng, S. Reddy","doi":"10.1109/ATS.2006.9","DOIUrl":"https://doi.org/10.1109/ATS.2006.9","url":null,"abstract":"Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"131 25","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120820495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter 存在采样时钟抖动的增强A/D转换器信噪比测试
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.47
Shalabh Goyal, A. Chatterjee, Yanan Shieh
{"title":"Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter","authors":"Shalabh Goyal, A. Chatterjee, Yanan Shieh","doi":"10.1109/ATS.2006.47","DOIUrl":"https://doi.org/10.1109/ATS.2006.47","url":null,"abstract":"Random jitter, present in the clock that is used for sampling the test input signal, is a major impediment to the signal-to-noise-ratio (SNR) measurement accuracy using the conventional dynamic testing methodology. However, most low cost testers do not provide the low-jitter clock required for SNR measurement of high-resolution and high-speed A/D converters. This paper presents a test methodology to estimate the SNR of high-performance A/D converters accurately in the presence of sampling clock jitter. The proposed approach uses the \"locked-histogram\" technique to gather the statistical data on the aperture uncertainty of the device-under-test. It further correlates the data obtained from the locked-histogram technique to the true SNR of the device-under-test. The proposed approach was simulated using Matlab models and validated by performing the hardware experiments. The results show an accuracy of 0.1dB in SNR estimation using the proposed test methodology","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126059969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology IEEE 1149.6边界扫描合成的ASIC方法自动化
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.32
Brian Foutz, V. Chickermane, Bing-Hung Li, Harry Linzer, Gary Kunselman
{"title":"Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology","authors":"Brian Foutz, V. Chickermane, Bing-Hung Li, Harry Linzer, Gary Kunselman","doi":"10.1109/ATS.2006.32","DOIUrl":"https://doi.org/10.1109/ATS.2006.32","url":null,"abstract":"This paper describes an automated methodology to insert IEEE 1149.6 boundary scan in a production ASIC environment. The methodology includes updating the ASIC library to support the new test receiver component, updating the TAP controller logic and boundary cells, and finally providing support for embedded high speed I/O logic. Results from several industrial designs and example circuits are shown. These examples include multi-GHz serial I/O such as those used with serial ATA and PCI-Express","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128528498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Spectral RTL Test Generation for Gate-Level Stuck-at Faults 门级卡在故障的频谱RTL测试生成
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.71
Nitin Yogi, V. Agrawal
{"title":"Spectral RTL Test Generation for Gate-Level Stuck-at Faults","authors":"Nitin Yogi, V. Agrawal","doi":"10.1109/ATS.2006.71","DOIUrl":"https://doi.org/10.1109/ATS.2006.71","url":null,"abstract":"We model RTL faults as stuck-at faults on primary inputs, primary outputs, and flip-flops. Tests for these faults are analyzed using Hadamard matrices for Walsh functions and random noise level at each primary input. This information then helps generate vector sequences. At the gate-level, a fault simulator and an integer linear program (ILP) compact the test sequences. We give results for four ITC'99 and four ISC AS'89 benchmark circuits, and an experimental processor. The RTL spectral vectors performed equally well on multiple gate-level implementations. Compared to a gate-level ATPG, RTL vectors produced similar or higher coverage in shorter CPU times","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129224632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Power-Aware Test Data Compression for Embedded IP Cores 嵌入式IP核的功耗感知测试数据压缩
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.66
N. Badereddine, Zhanglei Wang, P. Girard, K. Chakrabarty, S. Pravossoudovitch, C. Landrault
{"title":"Power-Aware Test Data Compression for Embedded IP Cores","authors":"N. Badereddine, Zhanglei Wang, P. Girard, K. Chakrabarty, S. Pravossoudovitch, C. Landrault","doi":"10.1109/ATS.2006.66","DOIUrl":"https://doi.org/10.1109/ATS.2006.66","url":null,"abstract":"Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127909955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding 时延故障数据的交错统计编码高效测试压缩
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.56
K. Namba, Hideo Ito
{"title":"Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding","authors":"K. Namba, Hideo Ito","doi":"10.1109/ATS.2006.56","DOIUrl":"https://doi.org/10.1109/ATS.2006.56","url":null,"abstract":"This paper proposes a method providing efficient test compression for delay fault testing using enhanced scan design. In the proposed method, the initial and transition vectors of test data are interleaved before test compression using statistical coding. This paper also shows test architecture for delay fault testing using the proposed method. The proposed method is experimentally evaluated from the viewpoint of compression rates. For robust testable path delay fault testing on 11 out of 23 ISCA589 benchmark circuits, the combination of Huffman coding and the proposed method provides higher compression rates than Huffman coding without the proposed method, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC)","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121776129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Not all Delay Tests Are the Same - SDQL Model Shows True-Time 并非所有延迟测试都是相同的- SDQL模型显示的是实时的
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.62
A. Uzzaman, Mick Tegethoff, Bibo Li, K. McCauley, S. Hamada, Yasuo Sato
{"title":"Not all Delay Tests Are the Same - SDQL Model Shows True-Time","authors":"A. Uzzaman, Mick Tegethoff, Bibo Li, K. McCauley, S. Hamada, Yasuo Sato","doi":"10.1109/ATS.2006.62","DOIUrl":"https://doi.org/10.1109/ATS.2006.62","url":null,"abstract":"Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a statistical delay quality model (SDQM) model to estimate the statistical delay quality level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130197827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency 具有序列递归依赖的电阻式开放的特殊ATPG技术
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.17
M. Renovell, M. Comte, I. Polian, P. Engelke, B. Becker
{"title":"A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency","authors":"M. Renovell, M. Comte, I. Polian, P. Engelke, B. Becker","doi":"10.1109/ATS.2006.17","DOIUrl":"https://doi.org/10.1109/ATS.2006.17","url":null,"abstract":"This paper analyzes the electrical behaviour of resistive opens as a function of their unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that detection of the open by a given vector Ti recursively depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this recursive effect is presented and a specific ATPG strategy is proposed","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134483693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An External Test Approach for Network-on-a-Chip Switches 片上网络交换机的外部测试方法
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.23
J. Raik, V. Govind, R. Ubar
{"title":"An External Test Approach for Network-on-a-Chip Switches","authors":"J. Raik, V. Govind, R. Ubar","doi":"10.1109/ATS.2006.23","DOIUrl":"https://doi.org/10.1109/ATS.2006.23","url":null,"abstract":"Over the past few years, network-on-a-chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on general purpose design-for-testability (DFT) approaches and there is a lack of test algorithms dedicated to on-chip networks. The main contribution of this paper is a well-scalable external test method, where insertion of wrappers and scan paths will not be required. The paper proposes an external test method for NoC based on functional fault models, which targets single stuck-at faults in the network switches. Furthermore, 100 per cent of delay faults open and shorts between adjacent interconnection lines are covered by the method. The approach allows reaching higher fault coverage in comparison to the recent DFT based solutions","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116966782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format 下一步在卷扫描诊断:标准失败数据格式
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.79
A. Leininger, A. Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, R. Klingenberg, Wu Yang
{"title":"The Next Step in Volume Scan Diagnosis: Standard Fail Data Format","authors":"A. Leininger, A. Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, R. Klingenberg, Wu Yang","doi":"10.1109/ATS.2006.79","DOIUrl":"https://doi.org/10.1109/ATS.2006.79","url":null,"abstract":"The need for faster and more reliable yield ramp-up when introducing new CMOS technologies is driving the effort to acquire and analyze valuable information from production test, for the process of identification of yield detractors. This paper addresses a key step in the phase of \"industrialization\" of these processes: standardization. The objective of standardization is to enable a seamless flow for production integrated scan diagnosis in a multi-tool, multi-vendor environment. To make analysis of chips failing the production test more efficient, a process flow and a file format to store the failing response of the chips is proposed. This enables a smooth exchange of production test data from ATE to diagnosis, failure analysis, design and process","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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