Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology

Abstract

This paper describes an automated methodology to insert IEEE 1149.6 boundary scan in a production ASIC environment. The methodology includes updating the ASIC library to support the new test receiver component, updating the TAP controller logic and boundary cells, and finally providing support for embedded high speed I/O logic. Results from several industrial designs and example circuits are shown. These examples include multi-GHz serial I/O such as those used with serial ATA and PCI-Express