Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter

Abstract

Random jitter, present in the clock that is used for sampling the test input signal, is a major impediment to the signal-to-noise-ratio (SNR) measurement accuracy using the conventional dynamic testing methodology. However, most low cost testers do not provide the low-jitter clock required for SNR measurement of high-resolution and high-speed A/D converters. This paper presents a test methodology to estimate the SNR of high-performance A/D converters accurately in the presence of sampling clock jitter. The proposed approach uses the "locked-histogram" technique to gather the statistical data on the aperture uncertainty of the device-under-test. It further correlates the data obtained from the locked-histogram technique to the true SNR of the device-under-test. The proposed approach was simulated using Matlab models and validated by performing the hardware experiments. The results show an accuracy of 0.1dB in SNR estimation using the proposed test methodology