R. Sethuram, Seongmoon Wang, S. Chakradhar, M. Bushnell
{"title":"Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs","authors":"R. Sethuram, Seongmoon Wang, S. Chakradhar, M. Bushnell","doi":"10.1109/ATS.2006.88","DOIUrl":"https://doi.org/10.1109/ATS.2006.88","url":null,"abstract":"Since structured application specific integrated chip (ASIC) products require very short turn around time, long automatic test pattern generation (ATPG) run time is undesirable. Large structured ASICs often require a large number of test patterns to achieve the desired fault coverage. This paper presents the first test point insertion technique for structured ASICs that can reduce test set sizes and ATPG run time. Only unused flip-flops in the structured ASIC design are used to implement test points, so the proposed technique does not incur any hardware overhead. Since test points are inserted during a post-layout step, considering both timing and layout information, hence test points can be inserted without changing the existing layout or routing. Novel gain functions are defined that specifically quantify the reduction in test volume and test time to select the best signal lines for inserting test points. The gain function described in this paper is also applicable to regular cell based ASICs. The proposed test point insertion technique can be used in conjunction with any compression technique (Jas et al., 2003) to further reduce the test volume. Experimental results clearly demonstrate the effectiveness and scalability of the proposed technique. Using less than 1% of extra flip-flops and very little run time for test point insertion, test generation time was reduced by up 42.9% and test data volume by up to 25.9% while also achieving a near 100% fault efficiency for very large industrial (400K-5M signal lines) designs","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129983113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing","authors":"Armin Alaghi, Mahnaz Sadoughi Yarandi, Z. Navabi","doi":"10.1109/ATS.2006.25","DOIUrl":"https://doi.org/10.1109/ATS.2006.25","url":null,"abstract":"This paper presents BIST architecture for FPGA look-up table testing using a minimum number of logic elements for its ORA. The propagation of faults in the TPGs and CUTs is formulated so that the ORA can detect multiple faults by monitoring a single signal. At the cost of using more cells for the ORA, the granularity of error detection can be reduced to as low as one fault per five LUTs. The increase in the ORA overhead, and thus the untested FPGA areas, can be compensated by more configurations. We will show that 100% test coverage and a maximum granularity can be achieved simultaneously by a reasonable number of FPGA configurations","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130004149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs","authors":"Naghmeh Karimi, S. Mirkhani, Z. Navabi","doi":"10.1109/ATS.2006.48","DOIUrl":"https://doi.org/10.1109/ATS.2006.48","url":null,"abstract":"This paper proposes a novel and efficient method for RT level online testing. Our method makes every RT-level resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or latency overhead are due to concurrent operation of active and inactive resources. This method is evaluated by fault simulating several benchmark designs before and after applying the proposed algorithm. Experimental results show that after applying our method, online fault coverage is significantly improved","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"151 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131652832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"iDEN Phone System Test: An Automation Approach","authors":"M. A. Mazlan, Ong Kein Wei, Cindy Phang Sim Sim","doi":"10.1109/ATS.2006.54","DOIUrl":"https://doi.org/10.1109/ATS.2006.54","url":null,"abstract":"Global Software Group Malaysia (GSG) is the first MSC status company out of 676 MSC-status companies in Malaysia to achieve the SEI-CMM Level 5 in October 2001. SEI-CMM Level 5 is the highest level of process maturity in software engineering. iDENtrade Subscriber Group-Test, iSGT is a subset team under GSG Malaysia and actually it is an extension of the iDENtrade Subsriber Group System Test in Plantation, Florida. iSGT is a software testing team who involved in Motorola iDENtrade phone software system test","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115849186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test data compression based on clustered random access scan","authors":"Yu Hu, Cheng Li, Jia Li, Yin-He Han, Xiao-wei Li, Wei Wang, Hua-wei Li, Laung-Terng Wang, Xiao-Qing Wen","doi":"10.1109/ATS.2006.74","DOIUrl":"https://doi.org/10.1109/ATS.2006.74","url":null,"abstract":"We proposed clustered random access scan (CRAS) architecture to reduce test data volume. CRAS makes use of the compatibility of the test stimuli to cluster the scan cells, and assigns every cluster a unique address. The compression ratio upper bound of CRAS is analyzed based on the random graph theory. Experimental results on ISCAS'89 benchmarks and two industry designs show that the proposed CRAS architecture can yield on average 67.3% reduction in test data volume, with reasonable area and routing overhead than scan design","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto
{"title":"Memory Fault Simulator for Static-Linked Faults","authors":"A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/ATS.2006.59","DOIUrl":"https://doi.org/10.1109/ATS.2006.59","url":null,"abstract":"Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked faults","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Diagnosis of delay faults due to resistive bridges, delay variations and defects","authors":"Lei Wang, S. Gupta, M. Breuer","doi":"10.1109/ATS.2006.43","DOIUrl":"https://doi.org/10.1109/ATS.2006.43","url":null,"abstract":"In this paper, we present the first diagnosis algorithm for combinational circuit blocks that considers all combinations of multiple gate/wire delay variations/defects and any single resistive bridge. One key component of the proposed algorithm is a new path-oriented effect-cause procedure to identify all possible suspects of above type that might have caused the timing errors observed during test. The second key component is an efficient data structure to represent the suspects. The third key component is a new algorithm to analyze passing tests to vindicate some of the suspects identified. This algorithm exploits the newly identified concept of fixed-but-unknown delays, i.e., the fact that during the period of diagnosis the values of all delay parameters for every gate and wire in the particular circuit under test remain fixed, although at values unknown to us. The final set of suspects reported by the algorithm is guaranteed to contain all possible causes of the observed timing errors. Experimental results on benchmark circuits show the effectiveness of the proposed approach","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121283037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test/Repair Area Overhead Reduction for Small Embedded SRAMs","authors":"Baosheng Wang, Q. Xu","doi":"10.1109/ATS.2006.76","DOIUrl":"https://doi.org/10.1109/ATS.2006.76","url":null,"abstract":"For current highly-integrated and memory-dominant system-on-a-chips (SoCs), especially for graphics and networking SoCs, the test/repair area overhead of embedded SRAMs (e-SRAMs) is a big concern. This paper presents various approaches to tackle this problem from a practical point of view. Without sacrificing at-speed testability, diagnosis capability and repairability, the proposed approaches consider partly sharing wrapper for identical memories, sharing memory BIST controllers for e-SRAMs embedded in different functional blocks, test responses compression for wide memories, and various repair strategies for e-SRAMs with different configurations. By combining the above approaches, the test/repair area overhead for e-SRAMs can be significantly reduced. For example, for one benchmark SoC used in our experiments, it can be reduced as much as 10% of the entire memory array","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132642263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Lin, Kun-Han Tsai, Chen Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, T. Aikyo
{"title":"Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects","authors":"X. Lin, Kun-Han Tsai, Chen Wang, M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, Y. Sato, S. Hamada, T. Aikyo","doi":"10.1109/ATS.2006.81","DOIUrl":"https://doi.org/10.1109/ATS.2006.81","url":null,"abstract":"In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range","authors":"Chung-Yi Li, Chia-Yuan Chou, Tsin-Yuan Chang","doi":"10.1109/ATS.2006.15","DOIUrl":"https://doi.org/10.1109/ATS.2006.15","url":null,"abstract":"In this paper, a jitter measurement circuit with its calibration scheme for measuring peak-to-peak jitters of clock is proposed and demonstrated. By applying the Vernier oscillators, the mismatching effect and area overhead are both reduced compared with conventional circuits using Vernier delay lines. With high resolution (7.98ps) and high speed (20.08ps/5k samples), the proposed circuit develops a tunable frequency range of input clock and improves the accuracy of the measurement results. The proposed circuit may be applied in multi-clocks' measurement","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121385655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}