Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs

Abstract

Since structured application specific integrated chip (ASIC) products require very short turn around time, long automatic test pattern generation (ATPG) run time is undesirable. Large structured ASICs often require a large number of test patterns to achieve the desired fault coverage. This paper presents the first test point insertion technique for structured ASICs that can reduce test set sizes and ATPG run time. Only unused flip-flops in the structured ASIC design are used to implement test points, so the proposed technique does not incur any hardware overhead. Since test points are inserted during a post-layout step, considering both timing and layout information, hence test points can be inserted without changing the existing layout or routing. Novel gain functions are defined that specifically quantify the reduction in test volume and test time to select the best signal lines for inserting test points. The gain function described in this paper is also applicable to regular cell based ASICs. The proposed test point insertion technique can be used in conjunction with any compression technique (Jas et al., 2003) to further reduce the test volume. Experimental results clearly demonstrate the effectiveness and scalability of the proposed technique. Using less than 1% of extra flip-flops and very little run time for test point insertion, test generation time was reduced by up 42.9% and test data volume by up to 25.9% while also achieving a near 100% fault efficiency for very large industrial (400K-5M signal lines) designs