静态链接故障的内存故障模拟器

2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI:10.1109/ATS.2006.59

A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto

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引用次数: 8

摘要

静态链接错误被认为是一类有趣的内存错误。它们影响其他故障行为的能力导致了故障效应的隐藏，使得测试算法的设计和验证成为一项非常复杂的任务。本文提出了一种针对全链故障的存储器故障模拟器体系结构

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Memory Fault Simulator for Static-Linked Faults

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked faults

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2006 15th Asian Test Symposium

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