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2006 15th Asian Test Symposium最新文献

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The Potential and Limitation of Probability-Based Combinational Equivalence Checking 基于概率的组合等价检验的潜力和局限性
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.80
Shih-Chieh Wu, Chun-Yao Wang, Jan-An Hsieh
{"title":"The Potential and Limitation of Probability-Based Combinational Equivalence Checking","authors":"Shih-Chieh Wu, Chun-Yao Wang, Jan-An Hsieh","doi":"10.1109/ATS.2006.80","DOIUrl":"https://doi.org/10.1109/ATS.2006.80","url":null,"abstract":"This paper presents a probability based approach to logic equivalence checking. First, a general probability assignment procedure is proposed to uniquely characterize output probability of a network. Thus, the equivalence of two networks can be asserted by the equality of output probabilities. To improve the efficiency of probability calculation, a new encoding scheme and operations are proposed. These encoding scheme and operations also solve the signal correlation issue during the output probability evaluation. As a result, an exact output probability of a network is successfully derived in one pass. Finally, the equivalence of internal gates between two networks are exploited to reduce the number of required input assignments and improve the efficiency of our approach. In the experiments, our approach is compared with a BDD based approach in terms of CPU time and memory usage. The results disclose the potential and limitation of the probabilistic approach to logic equivalence checking","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128665256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of practical ATPG tool with flexible interface 具有灵活界面的实用ATPG工具的开发
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.40
Masayoshi Yoshimura, Y. Matsunaga
{"title":"Development of practical ATPG tool with flexible interface","authors":"Masayoshi Yoshimura, Y. Matsunaga","doi":"10.1109/ATS.2006.40","DOIUrl":"https://doi.org/10.1109/ATS.2006.40","url":null,"abstract":"An ATPG tool is constructed by many functions. For evaluating new idea of only one subfunction accurately, it is necessary to develop all functions of the ATPG tool. Many of efficient techniques like static learning don't satisfy all evaluation standards of ATPG tools. Effectiveness of these efficient techniques is according to the structure of circuits. In FLEETS, practical and open EDA tools include ATPG tool have been developed for evaluating new ideas. The purpose of developing these EDA tools is to provide environment that facilitates evaluating new ideas. An ATPG tool which has flexible interfaces is developed as a part of environment for developing EDA tools","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128472601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Soft Error Tolerant LUT Cascade Emulator 一个软容错LUT级联仿真器
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.16
H. Nakahara, Tsutomu Sasao
{"title":"A Soft Error Tolerant LUT Cascade Emulator","authors":"H. Nakahara, Tsutomu Sasao","doi":"10.1109/ATS.2006.16","DOIUrl":"https://doi.org/10.1109/ATS.2006.16","url":null,"abstract":"An LUT cascade emulator realizes an arbitrary sequential circuit. Given a sequential circuit, we convert the combinational part into one or more LUT cascades, and store LUT (cell) data into a memory in the LUT cascade emulator. The emulator evaluates multi-output logic functions by reading cell data sequentially. To improve the tolerance to soft errors, cell data in the memory are encoded by error correcting codes. Also, error-correcting circuits and checking circuits that periodically scan the memories are appended. When a soft error is detected, it removes the error by rewriting the correct data into the memory. To mask soft errors in flip-flops, a TMR (triple module redundancy) technique is employed. Our system detects a soft error in a single bit. Also, the mission time of the system is more than 1000times of time of an ordinary LUT cascade emulator","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DFT of the Cell Processor and its Impact on EDA Test Softwar 单元处理机的DFT及其对EDA测试软件的影响
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.41
L. Bushard, Nathan Chelstrom, S. Ferguson, B. Keller
{"title":"DFT of the Cell Processor and its Impact on EDA Test Softwar","authors":"L. Bushard, Nathan Chelstrom, S. Ferguson, B. Keller","doi":"10.1109/ATS.2006.41","DOIUrl":"https://doi.org/10.1109/ATS.2006.41","url":null,"abstract":"This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124271264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Diagnosis of Transistor Shorts in Logic Test Environment 逻辑测试环境中晶体管短路的诊断
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.44
Y. Higami, K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Y. Takamatsu
{"title":"Diagnosis of Transistor Shorts in Logic Test Environment","authors":"Y. Higami, K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Y. Takamatsu","doi":"10.1109/ATS.2006.44","DOIUrl":"https://doi.org/10.1109/ATS.2006.44","url":null,"abstract":"For deep-sub micron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. This paper presents a method of fault diagnosis for transistor shorts in combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe precisely the behavior of transistor shorts. Therefore, two types of transistor short models were defined and algorithms to address the diagnostic problem were developed. The novelty of the algorithms is that they use conventional stuck-at fault simulation methodologies to diagnose transistor level shorts. Experiments were conducted on benchmark circuits to demonstrate the effectiveness of the method","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121969754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking 使用带宽匹配和片上可变时钟测试具有硬核的分层片上网络系统
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.77
Chunsheng Liu
{"title":"Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking","authors":"Chunsheng Liu","doi":"10.1109/ATS.2006.77","DOIUrl":"https://doi.org/10.1109/ATS.2006.77","url":null,"abstract":"In this paper, the paper presents a testing scheme for hierarchical network-on-a-chip (NoC) system consisting of hard embedded cores using bandwidth matching. The authors show how bandwidth matching and on-chip clocking techniques can be used in NoC to adapt the hard cores to the network channel width. The authors use a cost function to represent the tradeoff between test time and area overhead. In case of a hierarchical architecture, the authors show that various configurations of a core can be modelled as a set of rectangles and rectangle packing can be used for optimized TAM design. Experimental results show that the proposed method can significantly reduce the overall cost","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130484341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the Replacement of Scan Chain Inputs by Primary Input Vectors 扫描链输入用主输入向量替换的研究
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.63
I. Pomeranz, S. Reddy
{"title":"On the Replacement of Scan Chain Inputs by Primary Input Vectors","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2006.63","DOIUrl":"https://doi.org/10.1109/ATS.2006.63","url":null,"abstract":"We show that the functionality of scan chain inputs sometimes exists in a circuit as part of its functional operation, and can be exhibited by applying specific primary input vectors. By relying on such functionality it is possible to hide scan chains as part of a solution that addresses security. It is also possible to reduce the number of external scan chain inputs that need to be added to the circuit as part of the scan implementation, or remove the need to multiplex primary inputs as scan chain inputs. We define inherent scan in functions to capture the functionality of scan chain inputs that exists in a circuit, and show that they can be computed effectively by simulation. We address the case where multiple scan chains are to be used for the circuit","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs 片上压缩的可扩展架构:选择和权衡
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.13
A. Uzzaman, B. Keller, V. Chickermane
{"title":"A Scalable Architecture for On-Chip Compression: Options and Trade-Offs","authors":"A. Uzzaman, B. Keller, V. Chickermane","doi":"10.1109/ATS.2006.13","DOIUrl":"https://doi.org/10.1109/ATS.2006.13","url":null,"abstract":"This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129817510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Enhanced SRAM BISR Design with Reduced Timing Penalty 一种减少时间损失的增强型SRAM BISR设计
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.22
Li-Ming Denq, Tzu-Chiang Wang, Cheng-Wen Wu
{"title":"An Enhanced SRAM BISR Design with Reduced Timing Penalty","authors":"Li-Ming Denq, Tzu-Chiang Wang, Cheng-Wen Wu","doi":"10.1109/ATS.2006.22","DOIUrl":"https://doi.org/10.1109/ATS.2006.22","url":null,"abstract":"Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the built-in self-test (BIST) circuit-only one multiplexer delay for both the inputs and outputs","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132312545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor 减少扫描测试数据量和时间:诊断友好的有限内存压缩器
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.69
Sverre Wichlund, E. Aas
{"title":"Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor","authors":"Sverre Wichlund, E. Aas","doi":"10.1109/ATS.2006.69","DOIUrl":"https://doi.org/10.1109/ATS.2006.69","url":null,"abstract":"As the latest process technologies are combined with steadily increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. This in turn may result in costly tester reloads and unacceptable test application times. In this paper the authors present a finite memory test response compactor (a class of compactors originally proposed in Rajski et al., 2003) which is diagnosis friendly. The latter is important to maintain throughput on the test floor (Stanojevic et. al., 2005, Leininger et. al., 2002). Yet, the compactor has comparable performance to other schemes Rajski et al., 2003, Mitra et al., 2004, Mitra et al., 2004) when it comes to `X' tolerance and aliasing","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131984714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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