Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking

Abstract

In this paper, the paper presents a testing scheme for hierarchical network-on-a-chip (NoC) system consisting of hard embedded cores using bandwidth matching. The authors show how bandwidth matching and on-chip clocking techniques can be used in NoC to adapt the hard cores to the network channel width. The authors use a cost function to represent the tradeoff between test time and area overhead. In case of a hierarchical architecture, the authors show that various configurations of a core can be modelled as a set of rectangles and rectangle packing can be used for optimized TAM design. Experimental results show that the proposed method can significantly reduce the overall cost