A Soft Error Tolerant LUT Cascade Emulator

Abstract

An LUT cascade emulator realizes an arbitrary sequential circuit. Given a sequential circuit, we convert the combinational part into one or more LUT cascades, and store LUT (cell) data into a memory in the LUT cascade emulator. The emulator evaluates multi-output logic functions by reading cell data sequentially. To improve the tolerance to soft errors, cell data in the memory are encoded by error correcting codes. Also, error-correcting circuits and checking circuits that periodically scan the memories are appended. When a soft error is detected, it removes the error by rewriting the correct data into the memory. To mask soft errors in flip-flops, a TMR (triple module redundancy) technique is employed. Our system detects a soft error in a single bit. Also, the mission time of the system is more than 1000times of time of an ordinary LUT cascade emulator