单元处理机的DFT及其对EDA测试软件的影响

2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI:10.1109/ATS.2006.41

L. Bushard, Nathan Chelstrom, S. Ferguson, B. Keller

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引用次数: 14

摘要

本文介绍了Cell处理器DFT的各个方面及其对用于处理它的EDA软件的影响。Cell处理器是一个非常复杂的多核设计，使用接近4 GHz的高频时钟驱动DFT决策，这在几个层面上具有重要意义。处理器必须支持逻辑BIST，内存BIST, OPMSR+， SerDes I/O-WRAP以及传统的基于扫描的ATPG，所有这些都使用自由运行的高速时钟

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DFT of the Cell Processor and its Impact on EDA Test Softwar

This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock

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2006 15th Asian Test Symposium

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