片上压缩的可扩展架构:选择和权衡

2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI:10.1109/ATS.2006.13

A. Uzzaman, B. Keller, V. Chickermane

{"title":"片上压缩的可扩展架构:选择和权衡","authors":"A. Uzzaman, B. Keller, V. Chickermane","doi":"10.1109/ATS.2006.13","DOIUrl":null,"url":null,"abstract":"This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Scalable Architecture for On-Chip Compression: Options and Trade-Offs\",\"authors\":\"A. Uzzaman, B. Keller, V. Chickermane\",\"doi\":\"10.1109/ATS.2006.13\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results\",\"PeriodicalId\":242530,\"journal\":{\"name\":\"2006 15th Asian Test Symposium\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 15th Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2006.13\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 15th Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2006.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本演示介绍了用于测试数据压缩的可扩展片上架构，它提供了一种灵活的方法来指定、编译、验证、生成测试和诊断具有上述嵌入式构建块的芯片。针对不同用户群体的特定需求的设计流程、选项和权衡将通过一些案例研究和结果进行介绍

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Scalable Architecture for On-Chip Compression: Options and Trade-Offs

This presentation describes a scalable on-chip architecture for test data compression that provides a flexible means to specify, compile, verify, generate tests and diagnose chips with the embedded building blocks described above. The design flow, options and trade-offs that address the specific requirements of different segments of the user community will be presented with some case studies and results

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2006 15th Asian Test Symposium

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