{"title":"Verification Methodology for Self-Repairable Memory Systems","authors":"Jin-Fu Li, Chun-Hsien Wu","doi":"10.1109/ATS.2006.87","DOIUrl":"https://doi.org/10.1109/ATS.2006.87","url":null,"abstract":"With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127964914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Expansion of Convolutional Compactors over Galois Field","authors":"M. Arai, S. Fukumoto, K. Iwasaki","doi":"10.1109/ATS.2006.49","DOIUrl":"https://doi.org/10.1109/ATS.2006.49","url":null,"abstract":"Convolutional compactors offer a promising technique of compacting test responses. In this study the authors expand the architecture of convolutional compactor onto a Galois field in order to improve compaction ratio as well as reduce X-masking probability, namely, the probability that an error is masked by unknown values. While each scan chain is independently connected by EOR gates in the conventional arrangement, the proposed scheme treats q signals as an element over GF (2q), and the connections are configured on the same field. The authors show the arrangement of the proposed compactors and the equivalent expression over GF (2). The authors then evaluate the effectiveness of the proposed expansion in terms of X-masking probability by simulations with uniform distribution of X-values, as well as reduction of hardware overheads. Furthermore, the authors evaluate a multi-weight arrangement of the proposed compactors for non-uniform X distributions","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Youbean Kim, DongSup Song, Kicheol Kim, Incheol Kim, Sungho Kang
{"title":"TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure","authors":"Youbean Kim, DongSup Song, Kicheol Kim, Incheol Kim, Sungho Kang","doi":"10.1109/ATS.2006.83","DOIUrl":"https://doi.org/10.1109/ATS.2006.83","url":null,"abstract":"Power of scan operation is dominant factor. This paper proposed the structure to reduce scan power totally. The total scan power reduction architecture uses a duplicated transition monitoring window and sub-scan chains. Experimental results show 60% transition reduction, 2-4% fault coverage improvement, and 25% scan-in and 26% scan-out transition by the TOSCA","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132494546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter","authors":"Jiun-Lang Huang","doi":"10.1109/ATS.2006.12","DOIUrl":"https://doi.org/10.1109/ATS.2006.12","url":null,"abstract":"In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for on-chip jitter tolerance testing applications. First, the period-tracking technique (Kuo and Huang, 2006) is utilized to derive the SJ frequency and amplitude information. Then, using the same design-for-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130808089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fanout-based fault diagnosis for open faults on pass/fail information","authors":"K. Yamazaki, Y. Takamatsu","doi":"10.1109/ATS.2006.50","DOIUrl":"https://doi.org/10.1109/ATS.2006.50","url":null,"abstract":"With the increasing of circuit density, the importance of locating open faults becomes larger. In recent years, built-in self test (BIST) is widely used to reduce test cost. Therefore, development of efficient fault diagnosis approach under BIST environment is much wanted. The paper proposed a fanout-based fault diagnosis approach for open faults on pass/fail information. Experimental results for ISCAS'85 and ITC'99 benchmark circuits show that the number of candidate faults becomes less than 2 at most cases by using error path tracing and multiple stuck-at fault simulator","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131020707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time","authors":"Zhanglei Wang, K. Chakrabarty","doi":"10.1109/ATS.2006.21","DOIUrl":"https://doi.org/10.1109/ATS.2006.21","url":null,"abstract":"Testing using n-detection test sets, in which a fault is detected by n (n > 1) input patterns, is being increasingly advocated to increase defect coverage. However, the data volume for an n-detection test set is often too large, resulting in high testing time and tester memory requirements. Test set selection is necessary to ensure that the most effective patterns are chosen from large test sets in a high-volume production testing environment. Test selection is also useful in a time-constrained wafer-sort environment. The authors use a probabilistic fault model and the theory of output deviations for test set selection - the metric of output deviation is used to rank candidate test patterns without resorting to fault grading. To demonstrate the quality of the selected patterns, experimental results were presented for resistive bridging faults and non-feedback zero-resistance bridging faults in the ISCAS benchmark circuits. Our results show that for the same test length, patterns selected on the basis of output deviations are more effective than patterns selected using several other methods","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121305507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Aldrich, R. Press, Takeo Kobayashi, Tatsuo Sakajiri
{"title":"Mentor Graphics DFT to Navigate Nanometer Test Challenges","authors":"G. Aldrich, R. Press, Takeo Kobayashi, Tatsuo Sakajiri","doi":"10.1109/ATS.2006.60","DOIUrl":"https://doi.org/10.1109/ATS.2006.60","url":null,"abstract":"Nanometer designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries. Semiconductor companies creating these nanometer designs are struggling with many issues that result from this shrinking complex design environment. Mentor graphics design-for-test is committed to helping you navigate these challenges to bringing a high quality product to market while reducing test cost","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123717202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Scan Design Technique Based on Pre-Synthesis Thru Functions","authors":"C. Y. Ooi, H. Fujiwara","doi":"10.1109/ATS.2006.11","DOIUrl":"https://doi.org/10.1109/ATS.2006.11","url":null,"abstract":"VLSI design has moved from bottom-up design approach to top-down design methodology with the aid of advanced computer-aided design (CAD) technology. This paper introduces a new scan design technique as a design-for-test (DFT) method for sequential circuits by exploiting the information of thru functions available at high-level description of the circuit. This DFT method reduces the number of flip-flops to be converted into scan flip-flops because some existing thru functions allow the flip-flops to be controllable from primary inputs or observable at primary outputs or both. Moreover, the DFT method can be applied to both structural RT-level circuits and gate-level circuits. The paper also presents a test generation procedure for the augmented sequential circuits using a combinational ATPG tool. The experimental results show the comparison of our DFT method with conventional scan techniques in terms of hardware overhead, test generation time, fault coverage, fault efficiency and test application time","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121109811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application","authors":"Y. Miura","doi":"10.1109/ATS.2006.39","DOIUrl":"https://doi.org/10.1109/ATS.2006.39","url":null,"abstract":"We have proposed a method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with unknown value. Finally, we show ATPG results that are suitable to the proposed method","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sanae Seike, Ken Namura, Y. Ohya, A. Uzzaman, Shinichi Arima, Dale Meehl, V. Chickermane, Azumi Kobayashi, S. Tanaka, Hiroyuki Adachi
{"title":"Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis","authors":"Sanae Seike, Ken Namura, Y. Ohya, A. Uzzaman, Shinichi Arima, Dale Meehl, V. Chickermane, Azumi Kobayashi, S. Tanaka, Hiroyuki Adachi","doi":"10.1109/ATS.2006.45","DOIUrl":"https://doi.org/10.1109/ATS.2006.45","url":null,"abstract":"As the industry fabricates devices with more on-chip circuitry using complex, advanced process technologies, the challenge to achieve satisfactory yield becomes more daunting (Madge, 2005). Leading-edge nanometer designs can be sensitive to inherent irregularity in sub-wavelength photolithography and variability in parametric characteristics often found in nanometer manufacturing environments. These factors often result in devices being fabricated with intermittent electrical performance problems. These types of systemic interactions (process-design) are the major factor in manufacturing yield loss in nanometer technology nodes. Failure diagnostics is being asked to identify these systemic defects, preferably during early product development, and provide enough information so that each defect is understood and can be addressed. This paper presents a case study, which empirically examines the challenges of achieving high yield during the early stage of wafer production with an examination of yield loss mechanisms. A proven methodology and model (volume yield diagnostics) for an economic justification enabling the timely identification of yield loss is discussed along with quick process methodology and analysis results based on real manufacturing data","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128206789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}