Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis

Abstract

As the industry fabricates devices with more on-chip circuitry using complex, advanced process technologies, the challenge to achieve satisfactory yield becomes more daunting (Madge, 2005). Leading-edge nanometer designs can be sensitive to inherent irregularity in sub-wavelength photolithography and variability in parametric characteristics often found in nanometer manufacturing environments. These factors often result in devices being fabricated with intermittent electrical performance problems. These types of systemic interactions (process-design) are the major factor in manufacturing yield loss in nanometer technology nodes. Failure diagnostics is being asked to identify these systemic defects, preferably during early product development, and provide enough information so that each defect is understood and can be addressed. This paper presents a case study, which empirically examines the challenges of achieving high yield during the early stage of wafer production with an examination of yield loss mechanisms. A proven methodology and model (volume yield diagnostics) for an economic justification enabling the timely identification of yield loss is discussed along with quick process methodology and analysis results based on real manufacturing data