A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter

Abstract

In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for on-chip jitter tolerance testing applications. First, the period-tracking technique (Kuo and Huang, 2006) is utilized to derive the SJ frequency and amplitude information. Then, using the same design-for-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique