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2006 15th Asian Test Symposium最新文献

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Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition 扫描矢量分解有效利用ATE矢量重复压缩
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.46
Jinkyu Lee, N. Touba
{"title":"Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition","authors":"Jinkyu Lee, N. Touba","doi":"10.1109/ATS.2006.46","DOIUrl":"https://doi.org/10.1109/ATS.2006.46","url":null,"abstract":"Previous approaches for utilizing ATE vector repeat are based on identifying runs of repeated scan data and directly generating that data using ATE vector repeat. Each run requires a separate vector repeat instruction, so the amount of compression is limited by the amount of ATE instruction memory available and the length of the runs (which typically will be much shorter than the length of a scan vector). In this paper a new and more efficient approach is proposed for utilizing ATE vector repeat. The scan vector sequence is partitioned and decomposed into a common sequence which is the same for an entire cluster of test cubes and a unique sequence that is different for each test cube. The common sequence can be generated very efficiently using ATE vector repeat. Experimental results demonstrate that the proposed approach can achieve much greater compression while using many fewer vector repeat instructions compared with previous methods","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124519707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters 用于数据转换器环回线性测试的统计数字均衡器
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.18
Hongjoong Shin, Jiseon Park, J. Abraham
{"title":"A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters","authors":"Hongjoong Shin, Jiseon Park, J. Abraham","doi":"10.1109/ATS.2006.18","DOIUrl":"https://doi.org/10.1109/ATS.2006.18","url":null,"abstract":"This paper presents a new built-in self test (BIST) method based on efficient digital equalization and spectral prediction techniques. The method enables accurate built-in characterization of the static performance parameters of data converters, and thus test and calibration costs can be significantly alleviated. Based on recent work on dynamic performance parameter characterization using a loopback test, the transfer function of a DAC in loopback mode is estimated with a spectral prediction technique and Chebyshev polynomials. A digital equalizer is designed to compensate for the non-linearity of the DAC in the pre-conversion stage, hence the ADC can be tested with the digitally calibrated analog signals. The digital equalizer overcomes accuracy limitations encountered in a traditional compensation technique, and thus a standard histogram test which may suffer from INL masking problems can be successfully applied. Simulation results are presented to validate the technique","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130412760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator 使用自由运行环形振荡器的时间-数字转换器的统计线性校准
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.72
J. Rivoir
{"title":"Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator","authors":"J. Rivoir","doi":"10.1109/ATS.2006.72","DOIUrl":"https://doi.org/10.1109/ATS.2006.72","url":null,"abstract":"Precise and fast time measurements have many applications in test that can be covered cost effectively by vernier delay line (VDL) based time-to-digital converters (TDC), implemented fully digitally in a modern CMOS process. Their inherent nonlinearity can be measured using a statistical code density method that relies on uniformly distributed time events. This paper discusses using a simple free-running ring oscillator with a choice of oscillation periods to generate sufficiently uniformly distributed calibration events. The uniformity requirement is shown to exclude a huge number of small oscillation period ranges, which are too coherent with the TDC's internal clock. A simple algorithm for checking suitability of a randomly chosen period from a non-perfectly stable, jittered ring oscillator is presented. Number and size of suitable period ranges are given analytically. For a VDL-based TDC design in 90 nm CMOS, a sufficiently large range of suitable oscillation periods will on average found after the third try; under worst case conditions with 99.99% confidence after trying 256 period choices. The proposed method enables TDCs with digital-only, fully autonomous calibration","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"113 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131942494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing 基于扫描的磁芯测试的低功耗导向测试修改和压缩技术
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.58
T. Hayashi, Naotsugu Ikeda, T. Shinogi, H. Takase, H. Kita
{"title":"Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing","authors":"T. Hayashi, Naotsugu Ikeda, T. Shinogi, H. Takase, H. Kita","doi":"10.1109/ATS.2006.58","DOIUrl":"https://doi.org/10.1109/ATS.2006.58","url":null,"abstract":"This paper proposes effective techniques for reducing not only test data volume but also scan-in transitions that are closely related to power dissipation. First, a new test smoothing algorithm was adopted that can reduce scan-in transitions through test vector modification. Second, a test compression method was proposed that can reduce test data volume while keeping down the increase of transitions as small as possible. The effectiveness of the proposed techniques was shown through experiments for ISCAS'89 benchmark circuits","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133857663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Practical Needs and Wants for Silicon Debug and Diagnosis 硅调试与诊断的实际需求
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.67
F. Muradali
{"title":"Practical Needs and Wants for Silicon Debug and Diagnosis","authors":"F. Muradali","doi":"10.1109/ATS.2006.67","DOIUrl":"https://doi.org/10.1109/ATS.2006.67","url":null,"abstract":"Summary form only given. New and efficient solutions for silicon debug and diagnosis will have a highly visible impact on productivity. From prototype turn-on to volume production, sources of difficulty can include, circuit complexity, packaging, physical access, schedule, missing tool capability and the traditional infrastructure development for just go/no-go testing. The goal of this panel is to identify precise topics to drive academic research and industrial development. It is a unique continuation of an IEEE Test Technology Committee effort to examine Silicon Debug & Diagnosis. As an initial step, the focus of the Silicon Debug and Diagnosis Workshop 2006 will be to generate a template cross-industry & cross-academia list of topics. This will be summarized and, with ATS audience participation, built upon","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ATPG for Dynamic Burn-In Test in Full-Scan Circuits 全扫描电路中动态老化测试的ATPG
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.27
A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto
{"title":"ATPG for Dynamic Burn-In Test in Full-Scan Circuits","authors":"A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/ATS.2006.27","DOIUrl":"https://doi.org/10.1109/ATS.2006.27","url":null,"abstract":"Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches for stress testing is high temperature burn-in. This work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in test","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121079344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Interconnect Open Defect Diagnosis with Physical Information 将开放缺陷诊断与物理信息互连
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.55
Wei Zou, Wu-Tung Cheng, S. Reddy
{"title":"Interconnect Open Defect Diagnosis with Physical Information","authors":"Wei Zou, Wu-Tung Cheng, S. Reddy","doi":"10.1109/ATS.2006.55","DOIUrl":"https://doi.org/10.1109/ATS.2006.55","url":null,"abstract":"Circuit behavior in the presence of interconnect open defects is affected by four major factors: the capacitances between the floating node and its neighboring nodes, the capacitances inside down-stream gates, initial trapped charge, and the threshold voltages of down-stream gates. Current interconnect open diagnosis methods either ignore all of these factors or consider a subset of them only. Thus the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present an interconnect open defect diagnosis method taking all these factors into account. Experiments conducted on benchmark circuits demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests 一种能在测试中调节IDDQ极限的BIC传感器
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.5
Masato Nakanishi, M. Hashizume, H. Yotsuyanagi, Y. Miura
{"title":"A BIC Sensor Capable of Adjusting IDDQ Limit in Tests","authors":"Masato Nakanishi, M. Hashizume, H. Yotsuyanagi, Y. Miura","doi":"10.1109/ATS.2006.5","DOIUrl":"https://doi.org/10.1109/ATS.2006.5","url":null,"abstract":"A built-in-current sensor (BIC sensor) is proposed whose IDDQ limit is able to be adjusted in each IC test. IDDQ tests of identical IDDQ limit can be realized with the current sensor, even if process variation occurs in the sensor. Also, an IDDQ test method is proposed for ICs, in each of which the BIC sensor is implemented. It is shown by some experiments that IDDQ limit of 10mu A will be able to be set and IDDQ test results based on the limit will be obtained by adjusting the limit for each IC if size variation of MOSs in the BIC sensor is less than 50%","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128754677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture 使用可重构扫描架构压缩确定性测试数据
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.35
H. Fujiwara, Jiaguang Sun, K. Chakrabarty, Yang Zhao, D. Xiang
{"title":"Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture","authors":"H. Fujiwara, Jiaguang Sun, K. Chakrabarty, Yang Zhao, D. Xiang","doi":"10.1109/ATS.2006.35","DOIUrl":"https://doi.org/10.1109/ATS.2006.35","url":null,"abstract":"The paper presents a new scan-based BIST technique, which is based on weighted scan enable signals and a scan forest architecture. A new testability measure is proposed to guide test pattern generation and produce patterns with fewer specified bits. This approach can effectively reduce the amount test data that needs to be stored on-chip. The proposed BIST method relies on a pseudorandom phase and a deterministic phase. The scan forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that an LFSR with size equal to the maximum number of the specified bits in the deterministic patterns for the random-resistant faults is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126124462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Study of N-Detectability in QCA Designs QCA设计中n -可探测性的研究
2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI: 10.1109/ATS.2006.73
B. Sikdar
{"title":"Study of N-Detectability in QCA Designs","authors":"B. Sikdar","doi":"10.1109/ATS.2006.73","DOIUrl":"https://doi.org/10.1109/ATS.2006.73","url":null,"abstract":"QCA (quantum dot cellular automata) are projected as the replacement of state-of-the-art CMOS designs. The wide acceptance of QCA based design of logic circuits demands analysis and estimation of defect coverage in such circuits. Conventional single stuck-at fault model has been commonly employed to identify the majority of defects at the logic level. However, stuck-at fault model may not fully capture the defects in QCA based designs but approximates the defects in such designs. This work evaluates the effectiveness of such state-of-the-art VLSI test mechanisms, and investigates the possibility of more defect coverage through N-detectability in QCA designs. An experimental set up has been created to study the test quality of such designs subject to a PRPG (pseudo-random-pattern generator). The results shown in the paper point to the fact that the conventional test technique for CMOS designs is also effective in QCA based designs","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125488101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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