{"title":"A Cost Effective Output Response Analyzer for sum - delta Modulation Based BIST Systems","authors":"Hao-Chiao Hong, Sheng-Chuan Liang","doi":"10.1109/ATS.2006.6","DOIUrl":"https://doi.org/10.1109/ATS.2006.6","url":null,"abstract":"A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123916529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"To Overtest Or Not To Overtest - More Questions Than Answers","authors":"I. Pomeranz","doi":"10.1109/ATS.2006.82","DOIUrl":"https://doi.org/10.1109/ATS.2006.82","url":null,"abstract":"Summary form only given. Overtesting occurs when a defect that would not be detected under functional operation conditions of a chip is detected due to non-functional conditions created during test application. More generally, overtesting refers to a failure of a chip that occurs during test application when the chip would operate correctly in functional mode. Thus, overtesting results in yield loss that is arguably unnecessary. Overtesting was reported under two-pattern scan-based tests applied for detecting transition faults. However, a wider range of test and defect types may be involved in overtesting. This talk reviews the existing methodologies for addressing overtesting. These methodologies can be broadly classified as based on redundant faults, or based on operation conditions. Methodologies based on redundant faults attempt to prevent faults, which do not affect the functional operation of the circuit, from being detected. Methodologies based on operation conditions attempt to ensure that non-functional operation, which is made possible by scan (or other design-for-testability logic), is avoided. Functional operation conditions in these methodologies are defined to occur when the circuit is in its reachable state space. For a synchronizable circuit, this includes every state that the circuit can visit after synchronization. This talk discusses the fundamental differences between these methodologies, their advantages and limitations. The differences between the methodologies can be seen from the following: 1) A detectable fault may have a test that detects it using a non-reachable state. 2) A redundant fault may become detectable under scan using a reachable state. The talk also raises questions related to overtesting, including the following: 1) Should overtesting (always) be avoided? 2) Should avoidance of overtesting focus only on transition (delay) faults and scan based tests? 3) Even if testing under functional operation conditions can achieve complete fault coverage, is the test set comprehensive enough? 4) Is there a preferred class of methodologies for avoiding overtesting?","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121021841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test Generation for Weak Resistive Bridges","authors":"Shahdad Irajpour, S. Gupta, M. Breuer","doi":"10.1109/ATS.2006.75","DOIUrl":"https://doi.org/10.1109/ATS.2006.75","url":null,"abstract":"An approach for testing weak resistive bridge targets is developed. The approach is based on defining and generating tests for a set of surrogates associated with each target. Either no or limited timing information is used during test generation. Experimental results show much higher coverage of targets and much lower complexity compared to those for crosstalk targets","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"12 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133552668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, M. Sanada
{"title":"Defect Diagnosis - Reasoning Methodology","authors":"Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, M. Sanada","doi":"10.1109/ATS.2006.36","DOIUrl":"https://doi.org/10.1109/ATS.2006.36","url":null,"abstract":"Diagnosis has become a crucial technology for early debugging and yield improvement. However, the conventional diagnosis methods are not good at locating the defects that are not precisely expressed only with logical fault models. In this paper, we propose a novel defect diagnosis methodology, which is based on the evaluation of defect behaviors using physical information. We examine suspected nodes' voltages by comparing with the observed responses of ATE. In the examination, we use \"defect activation\", which is an estimation method of defective nodes' voltages using physical information. Using this methodology, we introduce examples of diagnosis for open defects in a cell, and for interconnect open defects. Those successful results show the effectiveness of the defect diagnosis","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Scan Chain Adjustment Technology for Test Power Reduction","authors":"Jia Li, Yu Hu, Xiaowei Li","doi":"10.1109/ATS.2006.14","DOIUrl":"https://doi.org/10.1109/ATS.2006.14","url":null,"abstract":"Recently test power dissipation has become a more and more challenging issue. This paper proposes a technique to solve this problem through scan chain adjustment to eliminate unnecessary transitions in scan chains. An extended WTM (EWTM) metric is proposed to estimate dynamic power dissipation in circuit under test caused by transitions in test stimulus and response vectors. And the routing overhead of this methodology can be reduced through scan chain adjustment guided with our distance of EWTM (DEWTM) metric. Experimental results on ISCAS'89 benchmarks circuits show that the proposed approach can reduce average power dissipation during scan test by 72.2% on average, with negligible routing overhead","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Engelke, I. Polian, H. Manhaeve, M. Renovell, B. Becker
{"title":"Delta-IDDQ Testing of Resistive Short Defects","authors":"P. Engelke, I. Polian, H. Manhaeve, M. Renovell, B. Becker","doi":"10.1109/ATS.2006.37","DOIUrl":"https://doi.org/10.1109/ATS.2006.37","url":null,"abstract":"This paper addresses the efficiency of IDDQ and more specifically Delta- IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes","authors":"P. Wong, Jing Jiang","doi":"10.1109/ATS.2006.53","DOIUrl":"https://doi.org/10.1109/ATS.2006.53","url":null,"abstract":"Modern day mixed-signal designs present interesting challenges to DFT timing flow. In this paper, we will discuss how we devised a DFT timing flow utilizing dynamic simulation with a turn around time better than that of a STA tool. In particular, we describe a design where run time has been reduced from 28 hours to 7 minutes","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132809060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
YongJoon Kim, M. Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang
{"title":"An Effective Test Pattern Generation for Testing Signal Integrity","authors":"YongJoon Kim, M. Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang","doi":"10.1109/ATS.2006.20","DOIUrl":"https://doi.org/10.1109/ATS.2006.20","url":null,"abstract":"As more cores are integrated in a single chip with sophisticated process like nanotechnology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132622124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Application of BIST-Aided Scan Test for Real Chips","authors":"Hideaki Konishi, Michiaki Emori, Takahisa Hiraide","doi":"10.1109/ATS.2006.78","DOIUrl":"https://doi.org/10.1109/ATS.2006.78","url":null,"abstract":"It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127275648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure","authors":"Ming Li, Shiyi Xu, Jia-lin Cao, F. Ran, Shiwei Ma","doi":"10.1109/ATS.2006.7","DOIUrl":"https://doi.org/10.1109/ATS.2006.7","url":null,"abstract":"In this paper a pipelined carry-dependent sum adder with the self-checking structure is proposed. The adder includes four 8-bit carry-dependent sum adder (CDSA) , a 4-bit block carry look-ahead unit (BCLU) and a parity checker. The necessary area of the proposed adder is only about 3.85% over the traditional ripple carry adders, while the sum of the traditional adders is delayed by 39.2% with respect to the proposed adder for 32-bit implementation","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129795663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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