{"title":"Practical Needs and Wants for Silicon Debug and Diagnosis","authors":"F. Muradali","doi":"10.1109/ATS.2006.67","DOIUrl":"https://doi.org/10.1109/ATS.2006.67","url":null,"abstract":"Summary form only given. New and efficient solutions for silicon debug and diagnosis will have a highly visible impact on productivity. From prototype turn-on to volume production, sources of difficulty can include, circuit complexity, packaging, physical access, schedule, missing tool capability and the traditional infrastructure development for just go/no-go testing. The goal of this panel is to identify precise topics to drive academic research and industrial development. It is a unique continuation of an IEEE Test Technology Committee effort to examine Silicon Debug & Diagnosis. As an initial step, the focus of the Silicon Debug and Diagnosis Workshop 2006 will be to generate a template cross-industry & cross-academia list of topics. This will be summarized and, with ATS audience participation, built upon","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, M. Sanada
{"title":"Defect Diagnosis - Reasoning Methodology","authors":"Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, M. Sanada","doi":"10.1109/ATS.2006.36","DOIUrl":"https://doi.org/10.1109/ATS.2006.36","url":null,"abstract":"Diagnosis has become a crucial technology for early debugging and yield improvement. However, the conventional diagnosis methods are not good at locating the defects that are not precisely expressed only with logical fault models. In this paper, we propose a novel defect diagnosis methodology, which is based on the evaluation of defect behaviors using physical information. We examine suspected nodes' voltages by comparing with the observed responses of ATE. In the examination, we use \"defect activation\", which is an estimation method of defective nodes' voltages using physical information. Using this methodology, we introduce examples of diagnosis for open defects in a cell, and for interconnect open defects. Those successful results show the effectiveness of the defect diagnosis","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test Generation for Weak Resistive Bridges","authors":"Shahdad Irajpour, S. Gupta, M. Breuer","doi":"10.1109/ATS.2006.75","DOIUrl":"https://doi.org/10.1109/ATS.2006.75","url":null,"abstract":"An approach for testing weak resistive bridge targets is developed. The approach is based on defining and generating tests for a set of surrogates associated with each target. Either no or limited timing information is used during test generation. Experimental results show much higher coverage of targets and much lower complexity compared to those for crosstalk targets","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"12 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133552668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect Open Defect Diagnosis with Physical Information","authors":"Wei Zou, Wu-Tung Cheng, S. Reddy","doi":"10.1109/ATS.2006.55","DOIUrl":"https://doi.org/10.1109/ATS.2006.55","url":null,"abstract":"Circuit behavior in the presence of interconnect open defects is affected by four major factors: the capacitances between the floating node and its neighboring nodes, the capacitances inside down-stream gates, initial trapped charge, and the threshold voltages of down-stream gates. Current interconnect open diagnosis methods either ignore all of these factors or consider a subset of them only. Thus the diagnosis results from current procedures may not be as accurate as possible. In this paper, we present an interconnect open defect diagnosis method taking all these factors into account. Experiments conducted on benchmark circuits demonstrate that the proposed method can achieve a very high diagnosis accuracy and resolution","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Engelke, I. Polian, H. Manhaeve, M. Renovell, B. Becker
{"title":"Delta-IDDQ Testing of Resistive Short Defects","authors":"P. Engelke, I. Polian, H. Manhaeve, M. Renovell, B. Becker","doi":"10.1109/ATS.2006.37","DOIUrl":"https://doi.org/10.1109/ATS.2006.37","url":null,"abstract":"This paper addresses the efficiency of IDDQ and more specifically Delta- IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Scan Chain Adjustment Technology for Test Power Reduction","authors":"Jia Li, Yu Hu, Xiaowei Li","doi":"10.1109/ATS.2006.14","DOIUrl":"https://doi.org/10.1109/ATS.2006.14","url":null,"abstract":"Recently test power dissipation has become a more and more challenging issue. This paper proposes a technique to solve this problem through scan chain adjustment to eliminate unnecessary transitions in scan chains. An extended WTM (EWTM) metric is proposed to estimate dynamic power dissipation in circuit under test caused by transitions in test stimulus and response vectors. And the routing overhead of this methodology can be reduced through scan chain adjustment guided with our distance of EWTM (DEWTM) metric. Experimental results on ISCAS'89 benchmarks circuits show that the proposed approach can reduce average power dissipation during scan test by 72.2% on average, with negligible routing overhead","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes","authors":"P. Wong, Jing Jiang","doi":"10.1109/ATS.2006.53","DOIUrl":"https://doi.org/10.1109/ATS.2006.53","url":null,"abstract":"Modern day mixed-signal designs present interesting challenges to DFT timing flow. In this paper, we will discuss how we devised a DFT timing flow utilizing dynamic simulation with a turn around time better than that of a STA tool. In particular, we describe a design where run time has been reduced from 28 hours to 7 minutes","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132809060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
YongJoon Kim, M. Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang
{"title":"An Effective Test Pattern Generation for Testing Signal Integrity","authors":"YongJoon Kim, M. Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang","doi":"10.1109/ATS.2006.20","DOIUrl":"https://doi.org/10.1109/ATS.2006.20","url":null,"abstract":"As more cores are integrated in a single chip with sophisticated process like nanotechnology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132622124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Application of BIST-Aided Scan Test for Real Chips","authors":"Hideaki Konishi, Michiaki Emori, Takahisa Hiraide","doi":"10.1109/ATS.2006.78","DOIUrl":"https://doi.org/10.1109/ATS.2006.78","url":null,"abstract":"It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127275648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure","authors":"Ming Li, Shiyi Xu, Jia-lin Cao, F. Ran, Shiwei Ma","doi":"10.1109/ATS.2006.7","DOIUrl":"https://doi.org/10.1109/ATS.2006.7","url":null,"abstract":"In this paper a pipelined carry-dependent sum adder with the self-checking structure is proposed. The adder includes four 8-bit carry-dependent sum adder (CDSA) , a 4-bit block carry look-ahead unit (BCLU) and a parity checker. The necessary area of the proposed adder is only about 3.85% over the traditional ripple carry adders, while the sum of the traditional adders is delayed by 39.2% with respect to the proposed adder for 32-bit implementation","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129795663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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