An Effective Test Pattern Generation for Testing Signal Integrity

Abstract

As more cores are integrated in a single chip with sophisticated process like nanotechnology, testing signal integrity between the cores needs much effort due to complicate coupling effects. In this paper, we propose a novel test pattern generation method for testing signal integrity. Using this method, short and effective test patterns are generated with low hardware overhead. It can be used for self-test scheme and experimental results show the effectiveness of the proposed scheme