{"title":"性价比高的\\sum - \\delta调制型BIST系统输出响应分析仪","authors":"Hao-Chiao Hong, Sheng-Chuan Liang","doi":"10.1109/ATS.2006.6","DOIUrl":null,"url":null,"abstract":"A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Cost Effective Output Response Analyzer for \\\\sum - \\\\delta Modulation Based BIST Systems\",\"authors\":\"Hao-Chiao Hong, Sheng-Chuan Liang\",\"doi\":\"10.1109/ATS.2006.6\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications\",\"PeriodicalId\":242530,\"journal\":{\"name\":\"2006 15th Asian Test Symposium\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 15th Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2006.6\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 15th Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2006.6","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems
A cost effective output response analyzer (ORA) for Sigma-Delta modulation based BIST systems is presented. Instead of using fast Fourier transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Sigma-Delta modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
