bist辅助扫描检测在真芯片中的应用

2006 15th Asian Test Symposium Pub Date : 2006-11-20 DOI:10.1109/ATS.2006.78

Hideaki Konishi, Michiaki Emori, Takahisa Hiraide

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引用次数: 0

摘要

在大规模集成电路测试中，通常采用基于扫描的ATPG设计来实现高故障覆盖率。然而，随着设计复杂性的增加，测试成本也随之显著增加。为了降低测试成本，我们提出了一种新的方法——bist辅助扫描测试(BAST)。此后，我们将该方法应用于约200个芯片，结果非常成功，在减少设计流程影响的情况下降低了测试成本

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The Application of BIST-Aided Scan Test for Real Chips

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact

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2006 15th Asian Test Symposium

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