Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture

Abstract

The paper presents a new scan-based BIST technique, which is based on weighted scan enable signals and a scan forest architecture. A new testability measure is proposed to guide test pattern generation and produce patterns with fewer specified bits. This approach can effectively reduce the amount test data that needs to be stored on-chip. The proposed BIST method relies on a pseudorandom phase and a deterministic phase. The scan forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that an LFSR with size equal to the maximum number of the specified bits in the deterministic patterns for the random-resistant faults is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method