Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator

Precise and fast time measurements have many applications in test that can be covered cost effectively by vernier delay line (VDL) based time-to-digital converters (TDC), implemented fully digitally in a modern CMOS process. Their inherent nonlinearity can be measured using a statistical code density method that relies on uniformly distributed time events. This paper discusses using a simple free-running ring oscillator with a choice of oscillation periods to generate sufficiently uniformly distributed calibration events. The uniformity requirement is shown to exclude a huge number of small oscillation period ranges, which are too coherent with the TDC's internal clock. A simple algorithm for checking suitability of a randomly chosen period from a non-perfectly stable, jittered ring oscillator is presented. Number and size of suitable period ranges are given analytically. For a VDL-based TDC design in 90 nm CMOS, a sufficiently large range of suitable oscillation periods will on average found after the third try; under worst case conditions with 99.99% confidence after trying 256 period choices. The proposed method enables TDCs with digital-only, fully autonomous calibration