Verification Methodology for Self-Repairable Memory Systems

Abstract

With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors