{"title":"扩频时钟发生器的数字BIST方法","authors":"Maohsuan Chou, Jen-Chien Hsu, C. Su","doi":"10.1109/ATS.2006.8","DOIUrl":null,"url":null,"abstract":"In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small","PeriodicalId":242530,"journal":{"name":"2006 15th Asian Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Digital BIST Methodology for Spread Spectrum Clock Generators\",\"authors\":\"Maohsuan Chou, Jen-Chien Hsu, C. Su\",\"doi\":\"10.1109/ATS.2006.8\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small\",\"PeriodicalId\":242530,\"journal\":{\"name\":\"2006 15th Asian Test Symposium\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 15th Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2006.8\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 15th Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2006.8","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Digital BIST Methodology for Spread Spectrum Clock Generators
In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small