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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A High-Efficiency Charge Pump for AMOLED Display Driver IC 一种用于AMOLED显示驱动IC的高效电荷泵
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620201
Junkai Zhang, Zunkai Huang, Quanze Li, Xinyao Zhang, Li Tian, Yongxin Zhu, Hui Wang, Songlin Feng
{"title":"A High-Efficiency Charge Pump for AMOLED Display Driver IC","authors":"Junkai Zhang, Zunkai Huang, Quanze Li, Xinyao Zhang, Li Tian, Yongxin Zhu, Hui Wang, Songlin Feng","doi":"10.1109/ASICON52560.2021.9620201","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620201","url":null,"abstract":"In this paper, we propose a novel efficiency-optimized charge pump for AMOLED display driver IC. In our design, we not only present a switching-voltage dynamic adjustment technique, but also utilize a dynamic biasing method to minimize the on-resistance of the switches, and improve the efficiency of the proposed charge pump. To verified our design, a prototype charge pump has been fabricated by Nuvoton 0.35-μm 2P3M BCD process. The experimental results show that when the values of load current are respectively 0mA, 60mA and 120mA, the efficiencies of our proposed charge pump are effectively improved by 17.78%, 18.46%, and 18.6% compared to the conventional charge pump.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127282451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Combined-solvent engineering of HPbI3 for efficient FAPbI3 perovskite solar cells 高效FAPbI3钙钛矿太阳能电池中HPbI3的联合溶剂工程
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620316
Wentao Tang, Xudong Yang, Yi Zhao
{"title":"Combined-solvent engineering of HPbI3 for efficient FAPbI3 perovskite solar cells","authors":"Wentao Tang, Xudong Yang, Yi Zhao","doi":"10.1109/ASICON52560.2021.9620316","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620316","url":null,"abstract":"Hybrid organic−inorganic halide perovskite solar cells have experienced a rocket-rising in efficiency, reaching a certified value beyond 25%. Tremendous jobs have been done on the CH3NH3PbI3 system to improve the efficiency. However, there are less studies have been done on the FAPbI3 system. And it is still difficult to form a pure α phase FAPbI3 with high surface coverage and big grain size at the same time. In this work, a combined-solvent engineering is proposed to deposit HPbI3 film with a roughness of only 5 nm. We obtained the uniform HPbI3 film by anti-solvent dripping during the spin of the DMF/NMP mixed solvent with equal molar ratio of PbI2 and hydrogen acid. Finally, it allows formation of high surface coverage, large grain size and pure α phase FAPbI3 perovskite films by the two-step method. A champion PCE of 18.2% as well as an average efficiency of 17.4% is finally achieved in the inverted planar cells with a high current density of 24.3 mA cm-2. The results illustrate this method is a convenient route for the deposition of pure FAPbI3 films, demonstrating great potential for higher efficiency of single junction device and further commercialization.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Three-Stage Comparator with High Speed and Low Power 一种高速低功耗三级比较器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620370
Jingqi Wang, Fan Ye, Junyan Ren
{"title":"A Three-Stage Comparator with High Speed and Low Power","authors":"Jingqi Wang, Fan Ye, Junyan Ren","doi":"10.1109/ASICON52560.2021.9620370","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620370","url":null,"abstract":"A three-stage comparator with two dynamic pre-amplifiers and a regenerative latch is proposed. The highlight of the proposed comparator is that a positive feedback pre-amplifier is added to the conventional two-stage comparator for higher gain and faster regenerative speed, which greatly suppresses the input-referred noise. In addition, the proposed comparator has almost no current flowing from the power supply to the ground, so it has extraordinary energy efficiency. Implemented in the 28-nm CMOS technology, the proposed comparator achieves a delay of 35.48 ps against 43.3 ps for the traditional comparator with a 25% reduction in power consumption. The resolution of the proposed comparator can be increased to 1 μV and the input-referred noise is reduced by 34% at a clock frequency of 10 GHz.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pixel Design of Ultra-high Speed CMOS Image Sensor 超高速CMOS图像传感器像素设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620252
P. Feng, Liyuan Liu, N. Wu
{"title":"Pixel Design of Ultra-high Speed CMOS Image Sensor","authors":"P. Feng, Liyuan Liu, N. Wu","doi":"10.1109/ASICON52560.2021.9620252","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620252","url":null,"abstract":"Ultra-high-speed (UHS) image sensors with time resolution from nano-second to micro-second are widely applied to research phenomena such as electric discharge, explosives, materials fracture. To realize UHS CMOS pixels with high time resolution and imaging quality, the photoelectrons in large pinned photo diode (PPD) must be transferred at very high velocity. This paper firstly presents an overview of two types of UHS CMOS pixels with multiple floating diffusion (MFD) or single floating diffusion (SFD). Then, two design examples with SFD at the edge/center of the photo-diode (PD) are also introduced to show the design of UHS CMOS pixel with large PPD.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122360116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Training, Programming, and Correction Techniques of Memristor-Crossbar Neural Networks with Non-Ideal Effects such as Defects, Variation, and Parasitic Resistance 具有缺陷、变异和寄生电阻等非理想效应的记忆电阻-交叉棒神经网络的训练、编程和校正技术
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620330
T. Nguyen, J. An, Seokjin Oh
{"title":"Training, Programming, and Correction Techniques of Memristor-Crossbar Neural Networks with Non-Ideal Effects such as Defects, Variation, and Parasitic Resistance","authors":"T. Nguyen, J. An, Seokjin Oh","doi":"10.1109/ASICON52560.2021.9620330","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620330","url":null,"abstract":"Memristor crossbars can be useful in realizing high-performance and low-power computing hardware especially for realizing edge-intelligence. Unfortunately, however, they have non-ideal effects such as memristor defects, conductance variation, parasitic resistance, etc. For compensating these non-ideal effects, various techniques should be used in implementing neural networks with memristor crossbars. More specifically, the memristor defects should be considered in the training process using defect map. The variation in programmed memristor’s conductance can be suppressed using the fine programming method of memristors. Moreover, to reduce errors of crossbar’s currents and voltages due to parasitic resistance, the correction circuit can be added to the crossbar peripheral. In this paper, these techniques are explained and verified to be able to minimize the recognition rate loss due to the non-ideal effects in the memristor crossbar.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130886099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS 10bit 1.6GS/s电流导向DAC, 40nm CMOS
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620411
Yukun Zhang, Xinpeng Xing
{"title":"A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS","authors":"Yukun Zhang, Xinpeng Xing","doi":"10.1109/ASICON52560.2021.9620411","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620411","url":null,"abstract":"In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulation results in 40nm CMOS show that for an input signal up to 550MHz, the SFDR and the SNR of the presented 1.6GS/s DAC achieve 67dB and 61dB respectively, with a maximum output current of 20mA. The DAC consumes 54mW power, from 1.1/2.2V supplies, and occupies 0.072mm2 core area.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127983594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE 一种宽量程12b 150MS/s P-SAR ADC，带开环残余放大器，用于超声AFE
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620280
Ziwei Li, Yutong Zhao, Guoting Wu, Fan Ye, Junyan Ren
{"title":"A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE","authors":"Ziwei Li, Yutong Zhao, Guoting Wu, Fan Ye, Junyan Ren","doi":"10.1109/ASICON52560.2021.9620280","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620280","url":null,"abstract":"A wide-range wide-band ADC is a crucial part of the high-frequency ultrasound imaging system analog front-end (AFE). This paper presents a wide input range 12b 150MS/s pipelined-SAR ADC design using a novel linearized open-loop subthreshold residue amplifier. The nonlinearity of the traditional subthreshold differential input pair is examined. Based on the examination, a new open-loop amplifier with a combined fully- and pseudo-differential input pair is proposed and mathematically analyzed. The proposed 12b 150MS/s pipelined-SAR ADC with the new residue amplifier is implemented and simulated using 28nm CMOS technology, attaining 74dB SFDR, 63dB SNDR and 14fJ/conv-step with a 1.44V full-scale range.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127992924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger 使用Schmitt触发器设计65nm可靠的近亚阈值标准电池
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620399
Jinliang Han, Yongzhong Wen, Yuejun Zhang, Pengjun Wang, Huihong Zhang
{"title":"A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger","authors":"Jinliang Han, Yongzhong Wen, Yuejun Zhang, Pengjun Wang, Huihong Zhang","doi":"10.1109/ASICON52560.2021.9620399","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620399","url":null,"abstract":"The researches of Near-threshold circuits pay much attention to performance and power consumption reduction. With the reduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptible to noise and process deviations. After researching low-power technology and Schmitt Trigger, we propose a semi-stacked standard cell circuit with high robustness. In order to optimize the logic gate, reduce the leakage current and improve the switch current ratio, we add a feedback transistor at the stack node of the circuit via the hysteresis effect and feedback mechanism of Schmitt Trigger. Then, we utilize the minimum width design method to improve the switching threshold and the driving current of the transistor. Our approach achieves the design of standard cell circuit under the TSMC 65nm CMOS process. The experimental results suggest that compared with previous works, our approach has the smallest coefficient of variance and the noise margin is improved about 11.5%-15.3%.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Superjunction MOSFET with Trench Schottky Contact and Embedded High-k Insulator for Excellent Reverse Recovery 具有沟肖特基触点和嵌入式高k绝缘体的超结MOSFET，具有优异的反向恢复
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620278
Rui Li, Mingmin Huang, Xi Zhang, Min Hu, Zhimei Yang, Yao Ma, M. Gong
{"title":"Superjunction MOSFET with Trench Schottky Contact and Embedded High-k Insulator for Excellent Reverse Recovery","authors":"Rui Li, Mingmin Huang, Xi Zhang, Min Hu, Zhimei Yang, Yao Ma, M. Gong","doi":"10.1109/ASICON52560.2021.9620278","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620278","url":null,"abstract":"A new superjunction MOSFET (SJ-MOSFET) with trench Schottky contact and embedded high-k insulator is proposed and investigated by TCAD simulations. In the reverse conduction state, the trench Schottky contact can easily collect electrons. So the hole injection efficiency of the body diode can be lowered to reduce the reverse recovery charge (Qrr). In addition, the high-k insulator is embedded in the p-pillar, which can increase the p-pillar resistance during reverse recovery so as to reduce the current recovery rate (dir/dt) from the peak reverse current (Irrm) to zero. Simulation results show that, the Qrr and dir/dt of the proposed SJ-MOSFET can be reduced by 46% and 71% respectively, compared with the conventional SJ-MOSFET.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Controlled domain wall directions within nanodevices integrated on the surface of LiNbO3 single crystals 在LiNbO3单晶表面集成的纳米器件内控制畴壁方向
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620490
Jun Jiang, Jie Sun, Chao Wang, A. Jiang
{"title":"Controlled domain wall directions within nanodevices integrated on the surface of LiNbO3 single crystals","authors":"Jun Jiang, Jie Sun, Chao Wang, A. Jiang","doi":"10.1109/ASICON52560.2021.9620490","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620490","url":null,"abstract":"Binary data in 1T1C and 2T2C non-volatile ferroelectric random access memories are represented by the switching and non-switching polarization charges based on a perovskite ferroelectric capacitor. However, downscaling of the cell dimensions reduces the amount of measurable polarization charges, thus the charge difference is no longer detected reliably in high-density memories. Erasable conductive nanosized domain walls (CDWs) in ferroelectrics can relieve the bottleneck of traditional ferroelectric memories. The binary ON-OFF states of the device accompany the creation and erasure of conductive walls between two antiparallel and parallel domains. Although many efforts have been contributed to the studies of the precise physical mechanism of domain wall conductivity and the fabrication process, there remain several challenges before its commercialization, among which how to increase the DW current density and to reduce the coercive voltage is critical. Here we show the route to arbitrarily control the conductive DW paths within the LiNbO3 nanodevices and the method to align the nanodevice against the polarization direction for the achievements of the best polarization retention and the minimum coercive field. In addition, a method to magnify the domain wall current by 3 times through the polarization alignment within the nanodevice has been demonstrated.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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