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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs 采用过中和技术和耦合线MCR匹配方法的c波段功率放大器在0.25-μm GaAs中用于5G通信
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620481
Zhiyang Zhang, Junyan Ren, Shunli Ma
{"title":"A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs","authors":"Zhiyang Zhang, Junyan Ren, Shunli Ma","doi":"10.1109/ASICON52560.2021.9620481","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620481","url":null,"abstract":"Wireless communication requires high transmission accuracy. To improve accuracy, high output power amplifier is needed in transmitter. In this paper, a C-band power amplifier with over-neutralization technique and coupled-line based Magnetic-Coupled Resonator (MCR) matching method is implemented in 0.25-μm GaAs technology. With the proposed matching method, the amplifier consumes a chip size of 1.88 mm2 including DC and RF pads, which is small for GaAs technology. Simulation results show the PA achieves 30-dB gain across 5.5-7 GHz with output power of 30-dBm.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127622648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ZnO Wheatstone bridge for UV light detection 紫外光检测用氧化锌惠斯通电桥
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620506
W. Peng, Xiaochuan Guo, Yahui Cai, Shuwen Guo, Xiaolong Zhao, Yong-ning He
{"title":"ZnO Wheatstone bridge for UV light detection","authors":"W. Peng, Xiaochuan Guo, Yahui Cai, Shuwen Guo, Xiaolong Zhao, Yong-ning He","doi":"10.1109/ASICON52560.2021.9620506","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620506","url":null,"abstract":"Traditional UV detectors suffer from the disadvantage of large size or could not operate well without expensive UV filter. Therefore, the development of UV detectors with advantages of small size, operational without UV filter, voltage output and easy to integrate with signal processing IC chips, is of significant importance. In this paper, a ZnO bridge type UV detection unit is proposed and realized, by using four ZnO metal-semiconductor-metal (MSM) structured photoconductive devices as the four bridge arm of the Wheatstone bridge. First, the key manufacture processes are investigated by using discrete ZnO MSM photoconductive devices. The fabrication processes of the ZnO MSM bridge arm, the SiO2 passivation layer, and the ZnO light-shielding layer are optimized. By using these optimized fabrication processes, a ZnO bridge type UV detection unit is successfully realized and its UV response characteristics are tested. The results indicate that, this UV detection unit could respond to UV light power ranging from 1 μW to 6 mW, owning volume smaller than 1 mm3. The results in this paper demonstrates that the proposed small sized ZnO bridge type UV detection unit could operate very well without expensive UV filter and output a voltage signal directly, and is easy to integrate with signal processing IC chips as an integrated ZnO UV detection chip.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm 能量感知视网膜:用于40nm人脸检测器的高能效边缘计算SOC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620286
Miao Sun, Yingjie Cao, Patrick Chiang
{"title":"Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm","authors":"Miao Sun, Yingjie Cao, Patrick Chiang","doi":"10.1109/ASICON52560.2021.9620286","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620286","url":null,"abstract":"In this work, an energy-awaring face detector is implemented in 40nm technology SoC. Based on the art-of-state face detector, a highest accuracy retinaface detector (91.4% average precision) on the WIDER FACE dataset is quantized in the int8 domain. For this neural network, an 8-bit CNN accelerator in a hybrid SOC architecture is designed to achieve an end-to-end face detector. The entire detector runs at 15fps with 66.67mw power per frame. Furthermore, redundant layers in this CNN are analyzed based on this performance. For different sizes of face, some calculations can be reduced with no loss brought to results. To address this improvement, this network is divided into three branches according to different sizes of faces in a single input image. Besides, a simple two-layer classifier is trained to determine the calculation graph in the current run and implemented on SOC. Finally, the face detector increases to 36fps, and energy power decreases to 27.78mw power per frame. This is the highest accuracy(85.8%) face detector hardware implementation on the WILDER FACE dataset.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115234102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology 基于模式相关数据级参考的28nm CMOS技术自适应DFE
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620339
Ai He, Weixin Gai, Kai Sheng, Ninghuang Li
{"title":"An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology","authors":"Ai He, Weixin Gai, Kai Sheng, Ninghuang Li","doi":"10.1109/ASICON52560.2021.9620339","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620339","url":null,"abstract":"The sign-sign least-mean-squares (SS-LMS) algorithm has been widely used to adapt both decision feedback equalizer (DFE) tap-coefficient and data-level reference. However, the adaptation process suffers from insufficient adaptation in the presence of pre-cursor inter-symbol-interference (ISI), resulting in eye-diagram destruction. A novel pattern-dependent data-level reference (PD-DLR) adaptation scheme is proposed to alleviate the problem. The PD-DLR is acquired by averaging the received signal when the adjacent two digitized data are both \"1\". With only an extra pattern filter working at low speed, the proposed scheme can be easily extended from existing adaptive DFE. Simulation results show about 20%, 43%, and 80% improvement in recovered eye height with normalized pre-cursor ISI of 0.14, 0.23, and 0.31 respectively and better noise immunity over its conventional counterparts. The effectiveness of the scheme is also verified in a 28 Gbps non-return to zero modulation adaptive DFE designed in 28 nm CMOS technology.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115765592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications 面向物联网双域应用的高效模块算术逻辑单元
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620531
Han Zeng, Wei Li, Tao Chen, Longmei Nan
{"title":"An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications","authors":"Han Zeng, Wei Li, Tao Chen, Longmei Nan","doi":"10.1109/ASICON52560.2021.9620531","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620531","url":null,"abstract":"Modular operation is the most basic operation in asymmetric cryptosystems. This paper proposes an improved modular multiplication algorithm and designs a Module Arithmetic Logic Unit (MALU) with high resource utilization, which realizes efficient dual-field modular operation through the multiplexing of basic circuits and the compression of number selection logic. This MALU is used to implement point multiplication of ECC and synthesized in CMOS 40nm process. Experimental results show that the highest frequency is 488 MHz with area of 101K gates. What’s more, the proposed circuit takes 0.267us and an average of 0.695us to finish 256-bit module multiplication and division respectively in GF(p)/GF(2m).","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115772004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Hardware Architecture for Adaptive Loop Filter in VVC Decoder VVC解码器中自适应环路滤波器的硬件结构
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620332
Xin Wang, Heming Sun, J. Katto, Yibo Fan
{"title":"A Hardware Architecture for Adaptive Loop Filter in VVC Decoder","authors":"Xin Wang, Heming Sun, J. Katto, Yibo Fan","doi":"10.1109/ASICON52560.2021.9620332","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620332","url":null,"abstract":"Adaptive Loop Filter (ALF) is a new technique proposed by the latest video coding standard Versatile Video Coding (VVC). To the best of our knowledge, this paper is the first implementation to design a hardware architecture of ALF in VVC decoder. The implementation reduces 60% of the memory access, saves approximately 50% of the hardware resources including adders and multipliers cost, increases the throughput and makes the hardware configurable for luma and chroma components. The synthesis result demonstrates that the architecture achieves a throughput of 4k@120fps and a maximum frequency of 367MHz under the TSMC 65nm process.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116034343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-Input-Impedance Amplifiers Design for Dry-Electrode Biopotential Acquisition: A Review 干电极生物电位采集的高输入阻抗放大器设计综述
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620463
Peizhuo Wang, Ting Yi, Zhiliang Hong
{"title":"High-Input-Impedance Amplifiers Design for Dry-Electrode Biopotential Acquisition: A Review","authors":"Peizhuo Wang, Ting Yi, Zhiliang Hong","doi":"10.1109/ASICON52560.2021.9620463","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620463","url":null,"abstract":"Wearable health monitoring devices are becoming more and more popular due to their improved user comfort and long-term measurement capability. Dry-electrode based interfaces are often limited by skin-electrode impedance, leading to signal attenuation and CMRR degradation. In order to solve these problems, the analog front-end amplifier must be designed with ultra-high input impedance. To achieve this target while maintaining balanced overall performance, it is necessary to investigate both optimized amplifier architectures and input-impedance boosting techniques. This paper reviews the key limiting factors to realize an ultra-high input impedance biopotential amplifiers, dominated by on-chip and off-chip parasitic capacitance from both circuit and system perspectives. We summarize and compare a number of high-impedance biopotential amplifier architectures, as well as various impedance boosting techniques, as the guidelines to develop the next generation dry-electrode biopotential signal acquisition ASICs and systems.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An On-chip Path Delay Measurement Sensor for Aging Monitoring 一种用于老化监测的片上路径延迟测量传感器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620372
Dongrong Zhang, Q. Ren, D. Su
{"title":"An On-chip Path Delay Measurement Sensor for Aging Monitoring","authors":"Dongrong Zhang, Q. Ren, D. Su","doi":"10.1109/ASICON52560.2021.9620372","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620372","url":null,"abstract":"With the development of technology, the reliability of integrated circuit (IC) is challenged by multiple aging mechanisms, which would increase the delay of ICs and result in timing violations. Hence, it is necessary to obtain the aging degradation rate of IC by measuring the delay change of the critical path. In this paper, an all-digital on-chip path delay measurement sensor is proposed. By measuring the critical path delay through IC lifetime, the aging degradation rate of IC can be obtained in real time. The proposed sensor has high measurement accuracy, and aging has a limited impact on it. Experiment result shows that the random measurement error is between 1.04ps -1.46ps during 1.5 years aging.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125871240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 800MS/s, 6.7b ENOB Bootstrap Switching S/H IC for Wideband Direct RF Sub-Sampling Receiver in 45 nm CMOS 一种用于45纳米CMOS宽带直接射频子采样接收器的800MS/s, 6.7b ENOB自举开关s /H IC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620243
Shuai Liu, Rui Yin, Hao Xu, Xiaoliang Shen, Na Yan
{"title":"An 800MS/s, 6.7b ENOB Bootstrap Switching S/H IC for Wideband Direct RF Sub-Sampling Receiver in 45 nm CMOS","authors":"Shuai Liu, Rui Yin, Hao Xu, Xiaoliang Shen, Na Yan","doi":"10.1109/ASICON52560.2021.9620243","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620243","url":null,"abstract":"Direct sampling RF receivers have become widely used in modern communication systems due to its agile operation. However, the sampling speed of the existing ADC can’t meet the requirements of direct sampling of RF signals. The application of sub-sampling technology is inevitable. The noise aliasing in the sub-sampling receiver puts forward higher requirements on the performance of the sampling and holding circuit. In this paper, we demonstrated a wideband S/H circuit for direct sub-sampling receiver in 45nm CMOS process. Bootstrap technology has been applied to improve SNDR performance by controlling the most important distortion source. With 800MHz sampling rate, the post-layout simulated results show that |S11| is lower than -30dB. The signal-to-noise and distortion ratio (SNDR) is higher than 42.33dB. The spurious-free dynamic range (SFDR) is higher than 45.06dB.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129757163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding 基于基数-8 Booth编码的节能近似浮点乘法器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620455
Rongyu Ding, Yi Guo, Heming Sun, S. Kimura
{"title":"Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding","authors":"Rongyu Ding, Yi Guo, Heming Sun, S. Kimura","doi":"10.1109/ASICON52560.2021.9620455","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620455","url":null,"abstract":"In applications such as digital signal processing and machine learning, the accuracy of internal operations is not so strict due to the limitation of human perception. Approximate computing has been focused as an effective way to trade off energy against accuracy. In this paper, a new type of approximate floating-point (FP) multiplier is proposed by applying radix-8 Booth encoding to the mantissa part. We devise the addition of the triple of multiplicand in radix-8 Booth encoding. Experimental results show the proposed design can achieve significant reduction in area, delay and power up to 66.48%, 23.39% and 69.02% while losing only 0.18% accuracy when compared with the IEEE-754 single precision FP multiplier. The proposed multipliers are applied to image smoothing and image compression and show negligible quality loss.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128186728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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