An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications

Modular operation is the most basic operation in asymmetric cryptosystems. This paper proposes an improved modular multiplication algorithm and designs a Module Arithmetic Logic Unit (MALU) with high resource utilization, which realizes efficient dual-field modular operation through the multiplexing of basic circuits and the compression of number selection logic. This MALU is used to implement point multiplication of ECC and synthesized in CMOS 40nm process. Experimental results show that the highest frequency is 488 MHz with area of 101K gates. What’s more, the proposed circuit takes 0.267us and an average of 0.695us to finish 256-bit module multiplication and division respectively in GF(p)/GF(2m).