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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS 用于22nm CMOS低功耗ADPLL的高分辨率数字-时间转换器辅助TA-TDC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620497
Liu Wang, Guojing Ye, Yumei Huang
{"title":"A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS","authors":"Liu Wang, Guojing Ye, Yumei Huang","doi":"10.1109/ASICON52560.2021.9620497","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620497","url":null,"abstract":"In this paper, a time amplifier (TA) based time-to-digital converter (TDC) as a fractional phase detector with high resolution and low power is presented in 22nm CMOS, which is a key module of an ADPLL for low power BLE application. A digital to time converter (DTC) is used for fractional phase prediction to reduce the dynamic range of TDC from at least one DCO cycle to dozens of picoseconds. On this basis, a TA based TDC with narrow dynamic range is proposed to achieve sub-1ps resolution. In addition, a gain digital calibration is added to the TA to increase the gain stability. At 1V supply voltage, the simulated time resolution of the TA-TDC is 0.86ps, and its peak DNL is -0.187LSB and INL is 0.466LSB. The power consumption of the TA-TDC is only 52.89μW at 28MS/s.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115692417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A High-Sensitivity, Low-Power Dual-Band RF Energy Harvesting and Managing System for Bio-Potential Acquisition 一种用于生物电位采集的高灵敏度、低功耗双频射频能量采集与管理系统
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620452
Yuyuan Tian, Lianxi Liu
{"title":"A High-Sensitivity, Low-Power Dual-Band RF Energy Harvesting and Managing System for Bio-Potential Acquisition","authors":"Yuyuan Tian, Lianxi Liu","doi":"10.1109/ASICON52560.2021.9620452","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620452","url":null,"abstract":"This paper proposes a high-sensitivity, low-power dual-band RF energy harvesting and managing system for bio-potential acquisition. The proposed dual-band RF energy harvester adopts the hybrid threshold voltage self-compensation technology and effectively improves the power conversion efficiency. A low-power voltage monitor is proposed to match the input power and the load power with the minimum current consumption. Moreover, the proposed power management unit (PMU) combines a voltage bootstrap circuit and a low-noise LDO to suppress the output ripple. The proposed chip was implemented in a 0.18-μm deep n-well CMOS process. The measured results show the dual-band RF energy harvester outputs a DC voltage of 1 V in two different frequency bands at the input power as low as -18.5 dBm. The PMU outputs stable DC voltages of 1 V and 1.8 V in working mode. In sleep mode, only the voltage monitor is working, and the average quiescent current is only 0.6 μA.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"49 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-bit Active Phase Shifter with Quadrature Outputs 具有正交输出的6位有源移相器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620409
Yujie Wu, Gang Zhang, Yongzhen Chen, Jiangfeng Wu
{"title":"A 6-bit Active Phase Shifter with Quadrature Outputs","authors":"Yujie Wu, Gang Zhang, Yongzhen Chen, Jiangfeng Wu","doi":"10.1109/ASICON52560.2021.9620409","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620409","url":null,"abstract":"A quadrature phase shifter with balanced QAF loading and improved accuracy in 28 nm CMOS technology is designed for a DC or low-IF receiver with double quadrature down-conversion. Quadrature all pass filter (QAF) with LC resonance at outputs achieves high quadrature accuracy over the whole phase shift range and a wide bandwidth. The designed digital-to-analog convertor (DAC) controls the amplitude of I/Q path and generates a phase shift angle covering 360°. The phase shifter operates in 24-30 GHz range. The phase shifter shows simulated rms phase error of < 2° and rms gain error of <0.2 dB at 24-30GHz, consuming 11.6mW.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127433292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM 氢退火对DRAM中外围PMOS NBTI和阵列晶体管GIDL的影响
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620242
Xiong Li, Huangxia Zhu, Xiaolin Guo, Kejun Mu, Peng Feng, Qi-An Xu, Blacksmith Wu, Kanyu Cao
{"title":"Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM","authors":"Xiong Li, Huangxia Zhu, Xiaolin Guo, Kejun Mu, Peng Feng, Qi-An Xu, Blacksmith Wu, Kanyu Cao","doi":"10.1109/ASICON52560.2021.9620242","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620242","url":null,"abstract":"The trade-off correlation between peripheral PMOS NBTI and Array transistors GIDL current received little attention, previously. We show experimental evidence that Hydrogen anneal will speed up the PMOS NBTI degradation, and reduce the Array transistors GIDL current, at the same time. In order to improve the PMOS NBTI immunity without damaging Array transistors electrical characters, we propose the increasing PG Fluorine implant, and discuss the NBTI improvement mechanism.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124940073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs 用于30μm节距低温红外fpga的高帧率、高线性度、低功耗DROIC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620518
Yuze Niu, Yuting Gu, Fengqing Liu, Fei Zhou, Shanzhe Yu, Wengao Lu, Yacong Zhang
{"title":"High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs","authors":"Yuze Niu, Yuting Gu, Fengqing Liu, Fei Zhou, Shanzhe Yu, Wengao Lu, Yacong Zhang","doi":"10.1109/ASICON52560.2021.9620518","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620518","url":null,"abstract":"This paper presents a pixel circuit with high frame rate, high linearity, and low power consumption. This pixel circuit is applied in a digital readout integrated circuit (DROIC) of 320×256 infrared focal plane array(IRFPA). The proposed single slope ADC is deployed in the proposed pixel circuit, which improves linearity and power consumption of the DROIC. The proposed pixel circuit is fabricated using 180nm 1P5M CMOS process with 30μm pixel pitch. Pixel power consumption is 406nW. Frame rate of the proposed DROIC is 1KHz. Nonlinearity of the quantization is lower than 0.8%.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123306794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pitch Device Design in 10nm-Class DRAM Process through DTCO 基于DTCO的10nm级DRAM工艺中螺距器件设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620445
Yanzhe Tang, Zhongming Liu, Weibing Shang, Fengqin Zhang, Bernard Wu, Zhong Kong, Hongwen Li, Hong Ma, Kanyu Cao
{"title":"Pitch Device Design in 10nm-Class DRAM Process through DTCO","authors":"Yanzhe Tang, Zhongming Liu, Weibing Shang, Fengqin Zhang, Bernard Wu, Zhong Kong, Hongwen Li, Hong Ma, Kanyu Cao","doi":"10.1109/ASICON52560.2021.9620445","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620445","url":null,"abstract":"The challenge for the pitch device design in Dynamic- Random-Access-Memory (DRAM) chip is increasing with the technology node continuing scaling down to 15nm and below. DTCO (Design-Technology-Co- Optimization is a must for designing pitch devices, which can fit into the word-line (WL) and bit-line (BL) pitch of the memory array, with satisfactory electrical and sufficient reliability performance, while occupies the smallest area. In this paper, we will show how we design the sub-wordline-driver (SWD) devices in a DRAM chip, taking into account of process limitations and variations, balancing the device between on/off performance and reliability requirements, and optimizing the circuits to reduce the hot-carrier-injection (HCI) stress, by utilizing different simulation tools which are calibrated with process data.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123736052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Demultiplexer Design in Quantum-dot Cellular Automata 量子点元胞自动机中一种高效的解复用器设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620355
Jian-Qiang Ni, Zhufei Chu
{"title":"An Efficient Demultiplexer Design in Quantum-dot Cellular Automata","authors":"Jian-Qiang Ni, Zhufei Chu","doi":"10.1109/ASICON52560.2021.9620355","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620355","url":null,"abstract":"QCA (quantum-dot cellular automata) has gained interest due to its high device density, high operating frequency, and low power consumption in recent years. Demultiplexers are widely used in data communications and signal routing fields. Traditional demultiplexing designs based on QCA technology have been implemented using distinct logic expressions based on majority gates and inverters. However, the implementation of inversion in QCA is costly. In this paper, we propose an efficient 1-2 demultiplexer structure in QCA technology using a Nand-Nor-Inverter (NNI) gate with complementary attributes. Hence, no inverters are required in the proposed 1-2 demultiplexer design. Moreover, we make use of the proposed 1-2 demultiplexer design as a basic module to design 1-4 demultiplexer. The experimental results show that our proposed demultiplexer has an average optimization of 15.27% in terms of QCA cell count, 19.44% in terms of the occupied area, 24.35% in terms of the cost function, and 8.33% in terms of delay compared to the state-of-the-art demultiplexer designs.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126718986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-powered Electrochromic Windows for Smart Homes Realized by Hybridizing Enhanced Perovskite Solar Cells 由杂交增强钙钛矿太阳能电池实现的智能家居自供电电致变色窗口
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620420
Jiabin Qi, Feilong Qiu, Yi Zhao
{"title":"Self-powered Electrochromic Windows for Smart Homes Realized by Hybridizing Enhanced Perovskite Solar Cells","authors":"Jiabin Qi, Feilong Qiu, Yi Zhao","doi":"10.1109/ASICON52560.2021.9620420","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620420","url":null,"abstract":"To reduce the cooling and lighting requirements in skyscrapers and increase residential comfort, smart window technologies have been developed to dynamically control the optical transmission of the visible and near-infrared light in the solar spectrum. In this work, we report self-powered electrochromic windows realized by hybridizing enhanced perovskite solar cells. The obtained electrochromic windows, which are powered by tandem solar cells with a voltage of ~2.0 V, exhibit a quick switching time of 9 s and an evident transmittance contrast (~70%) between the colored and bleached states. In practical use, the melting time per unit mass of ice sealed in a glass room could be extended by nearly 20%, exhibiting a good cooling effect. The hybrid system can accelerate the deployment of energy-saving technologies.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs 基于环形振荡器的16位像素级ADC，用于30μm螺距320 ×256 LWIR fpga
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620366
Yuze Niu, Bingxin Liu, Jiaqi Kong, Fei Zhou, Shanzhe Yu, Wengao Lu, Yacong Zhang, Zhongjian Chen
{"title":"A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs","authors":"Yuze Niu, Bingxin Liu, Jiaqi Kong, Fei Zhou, Shanzhe Yu, Wengao Lu, Yacong Zhang, Zhongjian Chen","doi":"10.1109/ASICON52560.2021.9620366","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620366","url":null,"abstract":"A low-power and high-dynamic range ADC-based 320×256 size digital readout integrated circuit for infrared focal plane arrays is proposed in this paper. Compared with the traditional structure, the proposed pixel-level ADC structure based on ring oscillator can achieve higher dynamic range and lower power consumption. The design is based on 0.18μm 1P5M CMOS process, and the pixel circuit pitch is 30μm. The simulation results show that the average power consumption of the proposed single pixel-level ADC is 1.36μW. The charge handling capacity of the pixel is 2.8Ge-; the dynamic range is 96.32dB, and the non-linearity is 0.76%.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization and Classification of Heavy Ion Induced Failures in FPGA-based Logical Circuits 基于fpga的逻辑电路中重离子诱导失效的表征与分类
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620393
S. Gao, C. Cai, Bingxu Ning, Ze He, Jie Liu
{"title":"Characterization and Classification of Heavy Ion Induced Failures in FPGA-based Logical Circuits","authors":"S. Gao, C. Cai, Bingxu Ning, Ze He, Jie Liu","doi":"10.1109/ASICON52560.2021.9620393","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620393","url":null,"abstract":"This paper proposes an accurate characterization and classification of failure modes and influences that occur in Static Random-Access Memory-based Field Programmable Gate Arrays (FPGAs). Five representative shift register chains with unhardened and redundancy hardened strategies are designed by utilizing logical resources of FPGAs. The heavy ion tests under different incident conditions are performed to classify and explore the failure impacts. The failed hardened circuits and 4-bit clustered errors reveal that the charge sharing effect and wide charge track area become a major concern for small feature size FPGAs. The local clock buffers and logical cells with different distances seriously affect the reliability of FPGA systems. In addition, the peripheral circuit induced different clustered and burst errors are successfully classified, and the worse failure modes and mechanisms are presented and discussed.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130338087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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