Pitch Device Design in 10nm-Class DRAM Process through DTCO

The challenge for the pitch device design in Dynamic- Random-Access-Memory (DRAM) chip is increasing with the technology node continuing scaling down to 15nm and below. DTCO (Design-Technology-Co- Optimization is a must for designing pitch devices, which can fit into the word-line (WL) and bit-line (BL) pitch of the memory array, with satisfactory electrical and sufficient reliability performance, while occupies the smallest area. In this paper, we will show how we design the sub-wordline-driver (SWD) devices in a DRAM chip, taking into account of process limitations and variations, balancing the device between on/off performance and reliability requirements, and optimizing the circuits to reduce the hot-carrier-injection (HCI) stress, by utilizing different simulation tools which are calibrated with process data.