Characterization and Classification of Heavy Ion Induced Failures in FPGA-based Logical Circuits

This paper proposes an accurate characterization and classification of failure modes and influences that occur in Static Random-Access Memory-based Field Programmable Gate Arrays (FPGAs). Five representative shift register chains with unhardened and redundancy hardened strategies are designed by utilizing logical resources of FPGAs. The heavy ion tests under different incident conditions are performed to classify and explore the failure impacts. The failed hardened circuits and 4-bit clustered errors reveal that the charge sharing effect and wide charge track area become a major concern for small feature size FPGAs. The local clock buffers and logical cells with different distances seriously affect the reliability of FPGA systems. In addition, the peripheral circuit induced different clustered and burst errors are successfully classified, and the worse failure modes and mechanisms are presented and discussed.