A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs

Yuze Niu, Bingxin Liu, Jiaqi Kong, Fei Zhou, Shanzhe Yu, Wengao Lu, Yacong Zhang, Zhongjian Chen
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Abstract

A low-power and high-dynamic range ADC-based 320×256 size digital readout integrated circuit for infrared focal plane arrays is proposed in this paper. Compared with the traditional structure, the proposed pixel-level ADC structure based on ring oscillator can achieve higher dynamic range and lower power consumption. The design is based on 0.18μm 1P5M CMOS process, and the pixel circuit pitch is 30μm. The simulation results show that the average power consumption of the proposed single pixel-level ADC is 1.36μW. The charge handling capacity of the pixel is 2.8Ge-; the dynamic range is 96.32dB, and the non-linearity is 0.76%.
基于环形振荡器的16位像素级ADC,用于30μm螺距320 ×256 LWIR fpga
本文提出了一种低功耗、高动态范围的基于adc的320×256尺寸红外焦平面阵列数字读出集成电路。与传统结构相比,本文提出的基于环形振荡器的像素级ADC结构可以实现更高的动态范围和更低的功耗。该设计基于0.18μm 1P5M CMOS工艺,像素电路间距为30μm。仿真结果表明,所提出的单像素级ADC的平均功耗为1.36μW。像素的电荷处理能力为2.8Ge-;动态范围为96.32dB,非线性度为0.76%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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