A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS

Abstract

In this paper, a time amplifier (TA) based time-to-digital converter (TDC) as a fractional phase detector with high resolution and low power is presented in 22nm CMOS, which is a key module of an ADPLL for low power BLE application. A digital to time converter (DTC) is used for fractional phase prediction to reduce the dynamic range of TDC from at least one DCO cycle to dozens of picoseconds. On this basis, a TA based TDC with narrow dynamic range is proposed to achieve sub-1ps resolution. In addition, a gain digital calibration is added to the TA to increase the gain stability. At 1V supply voltage, the simulated time resolution of the TA-TDC is 0.86ps, and its peak DNL is -0.187LSB and INL is 0.466LSB. The power consumption of the TA-TDC is only 52.89μW at 28MS/s.